tm1300 NXP Semiconductors, tm1300 Datasheet - Page 141
tm1300
Manufacturer Part Number
tm1300
Description
Tm-1300 Media Processor
Manufacturer
NXP Semiconductors
Datasheet
1.TM1300.pdf
(533 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- Current page: 141 of 533
- Download datasheet (7Mb)
Philips Semiconductors
9.5.2
TM1000 clock compatibility mode is provided so that
TM1000 audio software runs without changes. It should
NOT be used for new software development, due to a 3x
higher jitter. TM1000 mode is automatically entered
whenever FREQUENCY[31] = 0. In TM1000 mode,
AO_OSCLK frequency is set as follows:
9.6
The output of the DDS is always sent to the AO_OSCLK
output pin. This output is typically used as the 256f
384f
ers, such as the Philips SAA7322, or codecs such as the
AD1847, CS4218 or UD1340.
AO_WS and AO_SCK are sent to each external D/A con-
verter in the master mode.
AO_WS, the word strobe, determines the sample rate:
each active channel receives one sample for each
AO_WS period.
AO_SCK is the data bit clock. The number of AO_SCK
clocks in an AO_WS period is the number of data bits in
a serial frame required by the attached D/A converter.
AO_WS is a divider of the bit clock and is set using WS-
DIV to control the serial frame length. The number of bits
per frame is equal to WSDIV+1. There are some mini-
mum length requirements for a serial frame, refer to
Section
AO_SCK and AO_WS can be configured as input or out-
put, as determined by the SER_MASTER control field. If
set as output, AO_SCK can be set to a divider of the DDS
output frequency.
Whether set as input or output, the AO_SCK pin signal is
always used as the bit clock for parallel-serial conver-
sion. The AO_WS pin always acts as the trigger to start
the generation of a serial frame. AO_WS can similarly be
programmed using WSDIV to control the serial frame
length. The number of bits per frame is equal to WS-
DIV+1.
The preferred use of the clock system options is to use
AO_OSCLK as D/A master clock, and let the D/A con-
Figure 9-2. Definition of serial frame bit positions (POLARITY = 1, CLOCKEDGE = 0)
AO_WS
AO_SDx
AO_SCK
frame
s
f
system clock source for oversampling D/A convert-
AOSCK
FREQUENCY
n-1
CLOCK SYSTEM OPERATION
9.7.1.
30
TM1000 Clock Compatibility Mode
31
=
0
---------------------------------- -
SCKDIV
f
1
AOOSCLK
2
3
=
4
+
1
------------------------------- -
3 f
5
f
OSCLK
6
DSPCPU
7
SCKDIV
8
2
9
32
10
11
[ ,
12
0 255
13
14
]
15
s
or
16
17
frame
18
Table 9-3. AO MMIO Clock & Interface Control
verter be a timing slave of the serial interface
(SER_MASTER=1). This is important in view of compat-
ibility with future Trimedia devices, which may only sup-
port the AO unit as serial interface master.
Some D/A converters however, like the AD1847, provide
better SNR properties if they are configured as serial
master, with the AO unit as slave (SER_MASTER=0). As
illustrated by
converter that constructs the serial frame is oblivious to
which component is timing master.
9.7
The AO unit can generate data in a wide variety of serial
data framing conventions.
tion of a serial frame. If POLARITY=1, a frame starts with
a positive edge of the AO_WS signal. If POLARITY=0, a
serial frame starts with a negative edge on AO_WS. If
CLOCK_EDGE=0, the parallel to serial converter sam-
ples AO_WS on a positive clock edge transition, and out-
puts the first bit (bit 0) of a serial frame on the next falling
edge of AO_SCK.
If CLOCK_EDGE=1, the parallel to serial converter sam-
ples AO_WS on the negative edge of AO_SCK, while au-
dio data is output on the positive edge, i.e. the AO_SCK
polarity would be reversed with respect to
PRODUCT SPECIFICATION
n
SER_MASTER
FREQUENCY
SCKDIV
WSDIV
19
Field Name
20
21
SERIAL DATA FRAMING
22
23
24
Figure
25
0
1
The SER_MASTER bit should only be
changed while the AO unit is disabled, i.e.
TRANS_ENABLE = 0.
Sets the clock frequency emitted by the
AO_OSCLK output. RESET default 0.
Sets the divider used to derive AO_SCK
from AO_OSCLK. Set to 0..255, for divi-
sion by 1..256. RESET default 0.
Sets the divider used to derive AO_WS
from AO_SCK. Set to 0..511 for a serial
frame length of 1..512. RESET default 0.
26
9-1, the internal parallel to serial
27
TM1300 is the timing master over the
(RESET default), the D/A subsystem
is the timing master over the AO
serial interface. AO_SCK and
AO_WS act as inputs.
serial interface. AO_SCK and
AO_WS act as outputs. This mode is
required for 4,6 or 8 channel opera-
tion.
28
29
Figure 9-2
30
Description
31
0
1
illustrates the no-
2
frame
Figure
3
Audio Out
n+1
4
5
9-2.
6
7
9-3
Related parts for tm1300
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
Tm Supirbuck Highly Integrated 4a Wide-input Voltage, Synchronous Buck Regulator
Manufacturer:
International Rectifier Corp.
Datasheet:
Part Number:
Description:
NXP Semiconductors designed the LPC2420/2460 microcontroller around a 16-bit/32-bitARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG andembedded trace
Manufacturer:
NXP Semiconductors
Datasheet:
Part Number:
Description:
NXP Semiconductors designed the LPC2458 microcontroller around a 16-bit/32-bitARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG andembedded trace
Manufacturer:
NXP Semiconductors
Datasheet:
Part Number:
Description:
NXP Semiconductors designed the LPC2468 microcontroller around a 16-bit/32-bitARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG andembedded trace
Manufacturer:
NXP Semiconductors
Datasheet:
Part Number:
Description:
NXP Semiconductors designed the LPC2470 microcontroller, powered by theARM7TDMI-S core, to be a highly integrated microcontroller for a wide range ofapplications that require advanced communications and high quality graphic displays
Manufacturer:
NXP Semiconductors
Datasheet:
Part Number:
Description:
NXP Semiconductors designed the LPC2478 microcontroller, powered by theARM7TDMI-S core, to be a highly integrated microcontroller for a wide range ofapplications that require advanced communications and high quality graphic displays
Manufacturer:
NXP Semiconductors
Datasheet:
Part Number:
Description:
The Philips Semiconductors XA (eXtended Architecture) family of 16-bit single-chip microcontrollers is powerful enough to easily handle the requirements of high performance embedded applications, yet inexpensive enough to compete in the market for hi
Manufacturer:
NXP Semiconductors
Datasheet:
Part Number:
Description:
The Philips Semiconductors XA (eXtended Architecture) family of 16-bit single-chip microcontrollers is powerful enough to easily handle the requirements of high performance embedded applications, yet inexpensive enough to compete in the market for hi
Manufacturer:
NXP Semiconductors
Datasheet:
Part Number:
Description:
The XA-S3 device is a member of Philips Semiconductors? XA(eXtended Architecture) family of high performance 16-bitsingle-chip microcontrollers
Manufacturer:
NXP Semiconductors
Datasheet:
Part Number:
Description:
The NXP BlueStreak LH75401/LH75411 family consists of two low-cost 16/32-bit System-on-Chip (SoC) devices
Manufacturer:
NXP Semiconductors
Datasheet:
Part Number:
Description:
The NXP LPC3130/3131 combine an 180 MHz ARM926EJ-S CPU core, high-speed USB2
Manufacturer:
NXP Semiconductors
Datasheet:
Part Number:
Description:
The NXP LPC3141 combine a 270 MHz ARM926EJ-S CPU core, High-speed USB 2
Manufacturer:
NXP Semiconductors
Part Number:
Description:
The NXP LPC3143 combine a 270 MHz ARM926EJ-S CPU core, High-speed USB 2
Manufacturer:
NXP Semiconductors
Part Number:
Description:
The NXP LPC3152 combines an 180 MHz ARM926EJ-S CPU core, High-speed USB 2
Manufacturer:
NXP Semiconductors
Part Number:
Description:
The NXP LPC3154 combines an 180 MHz ARM926EJ-S CPU core, High-speed USB 2
Manufacturer:
NXP Semiconductors