s908qy2ad1vdwer Freescale Semiconductor, Inc, s908qy2ad1vdwer Datasheet - Page 105

• Manufacturer Part Number: s908qy2ad1vdwer
• Description: Mc68hc908qt4a Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

When DDRAx is a 1, reading PTA reads the PTAx data latch. When DDRAx is a 0, reading PTA reads
the logic level on the PTAx pin. The data latch can always be written, regardless of the state of its data
direction bit.
12.3.3 Port A Input Pullup Enable Register
The port A input pullup enable register (PTAPUE) contains a software configurable pullup device for each
of the port A pins. Each bit is individually configurable and requires the corresponding data direction
register, DDRAx, to be configured as input. Each pullup device is automatically and dynamically disabled
when its corresponding DDRAx bit is configured as output.
OSC2EN
PTAPUE[5:0] — Port A Input Pullup Enable Bits
Freescale Semiconductor
This read/write bit configures the OSC2 pin function when internal oscillator or RC oscillator option is
selected. This bit has no effect for the XTAL or external oscillator options.
These read/write bits are software programmable to enable pullup devices on port A pins.
1 = OSC2 pin outputs the internal or RC oscillator clock (BUSCLKX4)
0 = OSC2 pin configured for PTA4 I/O, having all the interrupt and pullup functions
1 = Corresponding port A pin configured to have internal pullup if its DDRA bit is set to 0
0 = Pullup device is disconnected on the corresponding port A pin regardless of the state of its
DDRA bit
— Enable PTA4 on OSC2 Pin
Reset:
Read:
Write:
Figure 12-4. Port A Input Pullup Enable Register (PTAPUE)
OSC2EN
READ DDRA
WRITE DDRA
WRITE PTA
READ PTA
Bit 7
0
= Unimplemented
MC68HC908QYA/QTA Family Data Sheet, Rev. 2
6
0
Figure 12-3
RESET
Figure 12-3. Port A I/O Circuit
PTAPUE5
5
0
does not apply to PTA2
PTAPUE4
NOTE
DDRAx
0
4
PTAx
PTAPUE3
3
0
PTAPUE2
2
0
PTAPUEx
PTAPUE1
1
0
PTAPUE0
PULLUP
Bit 0
0
PTAx
Port A
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