s908qy2ad1vdwer Freescale Semiconductor, Inc, s908qy2ad1vdwer Datasheet - Page 47

• Manufacturer Part Number: s908qy2ad1vdwer
• Description: Mc68hc908qt4a Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

ADCH[4:0] — Channel Select Bits
3.8.2 ADC10 Result High Register (ADRH)
This register holds the MSBs of the result and is updated each time a conversion completes. All other bits
read as 0s. Reading ADRH prevents the ADC10 from transferring subsequent conversion results into the
result registers until ADRL is read. If ADRL is not read until the after next conversion is completed, then
the intermediate conversion result will be lost. In 8-bit mode, this register contains no interlocking with
ADRL.
Freescale Semiconductor
If the bus frequency is less than the ADCK frequency, precise sample time for continuous conversions
cannot be guaranteed in short-sample mode (ADLSMP = 0). If the bus frequency is less than 1/11th
of the ADCK frequency, precise sample time for continuous conversions cannot be guaranteed in
long-sample mode (ADLSMP = 1).
When clear, the ADC10 will perform a single conversion (single conversion mode) each time ADSCR
is written (assuming the ADCH[4:0] bits do not decode all 1s).
The ADCH[4:0] bits form a 5-bit field that is used to select one of the input channels. The input
channels are detailed in
when the channel select bits are all set to 1. This feature allows explicit disabling of the ADC10 and
isolation of the input channel from the I/O pad. Terminating continuous conversion mode this way will
prevent an additional, single conversion from being performed. It is not necessary to set the channel
select bits to all 1s to place the ADC10 in a low-power state, however, because the module is
automatically placed in a low-power state when a conversion completes.
1 = Continuous conversion following a write to ADSCR
0 = One conversion following a write to ADSCR
1. If any unused or reserved channels are selected, the resulting conversion will
2. Requires LVI to be powered (LVIPWRD =0, in CONFIG1)
ADCH4
be unknown.
0
0
0
0
0
0
0
1
1
1
1
1
1
1
Table
ADCH3
MC68HC908QYA/QTA Family Data Sheet, Rev. 2
0
0
0
0
0
0
0
1
1
1
1
1
1
1
3-2. The successive approximation converter subsystem is turned off
Continuing through
Table 3-2. Input Channel Select
ADCH2
0
0
0
0
1
1
1
0
0
0
1
1
1
1
ADCH1
0
0
1
1
0
0
1
0
1
1
0
0
1
1
ADCH0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
BANDGAP REF
Low-power state
Input Select
Reserved
Reserved
Unused
Unused
Unused
V
V
AD0
AD1
AD2
AD3
AD4
AD5
REFH
REFL
(1)
(2)
Registers
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