s908ey8ad4cfjer Freescale Semiconductor, Inc, s908ey8ad4cfjer Datasheet - Page 53

• Manufacturer Part Number: s908ey8ad4cfjer
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

3.7.3 ADC Clock Register
This register selects the clock frequency for the ADC, selecting between modes of operation.
ADIV2:ADIV0 — ADC Clock Prescaler Bits
ADICLK — ADC Input Clock Select Bit
MODE1:MODE0 — Modes of Result Justification Bits
Freescale Semiconductor
ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate
the internal ADC clock.
ADICLK selects either bus clock or CGMXCLK as the input clock source to generate the internal ADC
clock. Reset selects CGMXCLK as the ADC clock source.
If the external clock (CGMXCLK) is equal to or greater than 1 MHz, CGMXCLK can be used as the
clock source for the ADC. If CGMXCLK is less than 1 MHz, use the PLL-generated bus clock as the
clock source. As long as the internal ADC clock is at f
20.10 Analog-to-Digital Converter (ADC)
MODE1:MODE0 selects among four modes of operation. The manner in which the ADC conversion
results will be placed in the ADC data registers is controlled by these modes of operation. Reset returns
right-justified mode.
1 = Internal bus clock
0 = External clock, CGMXCLK
00 = 8-bit truncation mode
01 = Right justified mode
10 = Left justified mode
11 = Left justified sign data mode
Address:
Reset:
Read:
Write:
f
ADIC
ADIV2
$003F
=
X = don’t care
Bit 7
0
ADIV2
CGMXCLK or bus frequency
Table 3-2
0
0
0
0
1
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
Figure 3-9. ADC Clock Register (ADCLK)
= Unimplemented
Address:
ADIV1
6
0
Table 3-2. ADC Clock Divide Ratio
ADIV[2:0]
ADIV1
shows the available clock configurations.
X
0
0
1
1
ADIV0
5
0
Characteristics.
ADIV0
ADICLK
X
0
1
0
1
4
0
ADIC
ADC input clock ÷ 1
ADC input clock ÷ 2
ADC input clock ÷ 4
ADC input clock ÷ 8
ADC input clock ÷ 16
MODE1
3
0
, correct operation can be guaranteed. See
ADC Clock Rate
MODE0
2
1
R
1
0
Bit 0
0
0
I/O Registers
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