s908ey8ad4cfjer Freescale Semiconductor, Inc, s908ey8ad4cfjer Datasheet - Page 82

• Manufacturer Part Number: s908ey8ad4cfjer
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Internal Clock Generator (ICG) Module
reference with comparators, whose outputs are fed to the digital loop filter. The dependence of these
outputs on the capacitor size, current reference, and voltage reference causes up to ±25 percent error in
f
8.3.2.4 Digital Loop Filter
The digital loop filter (DLF) uses the outputs of the frequency comparator to adjust the internal clock
(ICLK) clock period. The DLF generates the DCO divider control bits (DDIV[3:0]) and the DCO stage
control bits (DSTG[7:0]), which are fed to the DCO. The DLF first concatenates the DDIV and DSTG
registers (DDIV[3:0]:DSTG[7:0]) and then adds or subtracts a value dependent on the relative error in the
low-frequency base clock’s period, as shown in
operating at a V
maximum ($9FF) or below the minimum ($000). In both cases, the value for DDIV will be between $A and
$F. In this range, the DDIV value will be interpreted the same as $9 (the slowest condition). Recovering
from this condition requires subtracting (increasing frequency) in the normal fashion until the value is
again below $9FF. (If the desired value is $9xx, the value may settle at $Axx through $Fxx. This is an
acceptable operating condition.) If the error is less than ±5 percent, the internal clock generator’s filter
stable indicator (FICGS) is set, indicating relative frequency accuracy to the clock monitor.
8.3.3 External Clock Generator
The ICG also provides for an external oscillator or external clock source, if desired. The external clock
generator, shown in
82
NOM
1. x = Maximum error is independent of value in DDIV[3:0]. DDIV increments or decrements when an addition to DSTG[7:0]
of IBASE Compared
IBASE < 0.85 f
0.85 f
IBASE < 0.95 f
0.95 f
IBASE < 1.05 f
1.05 f
IBASE < 1.15 f
1.15 f
Frequency Error
.
IBASE < f
f
NOM
carries or borrows.
NOM
NOM
NOM
NOM
to f
< IBASE
NOM
< IBASE
< IBASE
< IBASE
< IBASE
NOM
NOM
NOM
NOM
NOM
DD
level which is out of specification, the DLF may attempt to use a value above the
Figure
DDVI[3:0]:DSTG[7:0]
8-4, contains an external oscillator amplifier and an external clock input path.
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
Table 8-1. Correction Sizes from DLF to DCO
–32 (–$020)
+32 (+$020)
Correction
–8 (–$008)
–1 (–$001)
+1 (+$001)
+8 (+$008)
Table
Maximum
Maximum
Maximum
Maximum
Maximum
Maximum
Minimum
Minimum
Minimum
Minimum
Minimum
Minimum
DDIV[3:0]:DSTG[7:0]
Current to New
8-1. In some extreme error conditions, such as
$xFF to $xDF
$xFF to $xFE
$xFE to $xFF
$xDF to $xFF
$xFF to $xF7
$xF7 to $xFF
$x20 to $x00
$x08 to $x00
$x01 to $x00
$x00 to $x01
$x00 to $x08
$x00 to $x20
(1)
–0.0625/17.0625
+0.0625/30.9375
–0.0625/31
+0.0625/17
–0.5/17.5
+0.5/30.5
–0.5/31
+0.5/17
Relative Correction
+2/29
+2/17
–2/31
–2/19
Freescale Semiconductor
in DCO
–0.202%
–0.366%
+0.202%
+0.368%
+1.64%
+2.94%
+11.8%
–6.45%
–10.5%
–1.61%
–2.86%
+6.90%