s908az32ag2cfue Freescale Semiconductor, Inc, s908az32ag2cfue Datasheet - Page 48

• Manufacturer Part Number: s908az32ag2cfue
• Description: M68hc08 Microcontrollers 8-bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Flash Memory
4.7 FLASH Program Operation
Programming of the FLASH memory is done on a row basis. A row consists of 64 consecutive bytes with
address ranges as follows:
During the programming cycle, make sure that all addresses being written to fit within one of the ranges
specified above. Attempts to program addresses in different row ranges in one programming cycle will
fail. Use this step-by-step procedure to program a row of FLASH memory.
In order to avoid program disturbs, the row must be erased before any byte on that row is programmed.
The FLASH Programming Algorithm Flowchart is shown in
48
10. Clear the PGM bit.
11. Wait for time, t
12. Clear the HVEN bit.
13. Wait for a time, t
1. Set the PGM bit in the FLASH Control Register (FLCR). This configures the memory for program
2. Read the FLASH Block Protect Register (FLBPR).
3. Write to any FLASH address within the row address range desired with any data.
4. Wait for time, t
5. Set the HVEN bit.
6. Wait for time, t
7. Write data byte to the FLASH address to be programmed.
8. Wait for time, t
9. Repeat step 7 and 8 until all the bytes within the row are programmed.
•
•
•
•
$XX00 to $XX3F
$XX40 to $XX7F
$XX80 to $XXBF
$XXC0 to $XXFF
operation and enables the latching of address and data programming.
B. While these operations must be performed in the order shown, other
unrelated operations may occur between the steps. Care must be taken
however to ensure that these operations do not access any address within
the FLASH array memory space such as the COP Control Register
(COPCTL) at $FFFF.
C. It is highly recommended that interrupts be disabled during
program/erase operations.
A. Programming and erasing of FLASH locations can not be performed by
code being executed from the same FLASH array.
B. While these operations must be performed in the order shown, other
unrelated operations may occur between the steps. Care must be taken
however to ensure that these operations do not access any address within
the FLASH array memory space such as the COP Control Register
(COPCTL) at $FFFF.
NVS
PGS
NVH
PROG
RCV
.
.
.
, after which the memory can be accessed in normal read mode.
.
MC68HC908AZ32A Data Sheet, Rev. 2
NOTE
NOTE
Figure
4-4.
Freescale Semiconductor