s908az32ag2cfue Freescale Semiconductor, Inc, s908az32ag2cfue Datasheet - Page 81

• Manufacturer Part Number: s908az32ag2cfue
• Description: M68hc08 Microcontrollers 8-bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

7.3.2.5 Low-Voltage Inhibit (LVI) Reset
The low-voltage inhibit module (LVI) asserts its output to the SIM when the V
voltage. The LVI bit in the SIM reset status register (SRSR) is set and a chip reset is asserted if the
LVIPWRD and LVIRSTD bits in the CONFIG-1 register are at logic zero. The RST pin will be held low until
the SIM counts 4096 CGMXCLK cycles after V
later, the CPU is released from reset to allow the reset vector sequence to occur. See
Voltage Inhibit
7.4 SIM Counter
The SIM counter is used by the power-on reset module (POR) and in stop mode recovery to allow the
oscillator time to stabilize before enabling the internal bus (IBUS) clocks. The SIM counter also serves as
a prescaler for the computer operating properly module (COP). The SIM counter overflow supplies the
clock for the COP module. The SIM counter is 12 bits long and is clocked by the falling edge of
CGMXCLK.
7.4.1 SIM Counter During Power-On Reset
The power-on reset module (POR) detects power applied to the MCU. At power-on, the POR circuit
asserts the signal PORRST. Once the SIM is initialized, it enables the clock generation module (CGM) to
drive the bus clock state machine.
7.4.2 SIM Counter During Stop Mode Recovery
The SIM counter also is used for stop mode recovery. The STOP instruction clears the SIM counter. After
an interrupt or reset, the SIM senses the state of the short stop recovery bit, SSREC, in the CONFIG-1
register. If the SSREC bit is a logic one, then the stop recovery is reduced from the normal delay of 4096
CGMXCLK cycles down to 32 CGMXCLK cycles. This is ideal for applications using canned oscillators
that do not require long start-up times from stop mode. External crystal applications should use the full
stop recovery time, that is, with SSREC cleared.
7.4.3 SIM Counter and Reset States
External reset has no effect on the SIM counter. See
free-running after all reset states. See
internal reset recovery sequences.
7.5 Program Exception Control
Normal, sequential program execution can be changed in three different ways:
Freescale Semiconductor
•
•
•
Interrupts
–
–
Reset
Break interrupts
Maskable hardware CPU interrupts
Non-maskable software interrupt instruction (SWI)
(LVI).
MC68HC908AZ32A Data Sheet, Rev. 2
7.3.2 Active Resets from Internal Sources
DD
rises above V
7.6.2 Stop Mode
LVIR
. Another sixty-four CGMXCLK cycles
for details. The SIM counter is
DD
voltage falls to the V
for counter control and
Chapter 14 Low
SIM Counter
LVII
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