s908az32ag2cfue Freescale Semiconductor, Inc, s908az32ag2cfue Datasheet - Page 91

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s908az32ag2cfue

Manufacturer Part Number
s908az32ag2cfue
Description
M68hc08 Microcontrollers 8-bit Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Chapter 8
Clock Generator Module (CGM)
8.1 Introduction
The CGM generates the crystal clock signal, CGMXCLK, which operates at the frequency of the crystal.
The CGM also generates the base clock signal, CGMOUT, from which the system clocks are derived.
CGMOUT is based on either the crystal clock divided by two or the phase-locked loop (PLL) clock,
CGMVCLK, divided by two. The PLL is a frequency generator designed for use with 1-MHz to 16-MHz
crystals or ceramic resonators. The PLL can generate an 8-MHz bus frequency without using high
frequency crystals.
8.2 Features
Features of the CGM include:
8.3 Functional Description
The CGM consists of three major submodules:
Figure 8-1
8.3.1 Crystal Oscillator Circuit
The crystal oscillator circuit consists of an inverting amplifier and an external crystal. The OSC1 pin is the
input to the amplifier and the OSC2 pin is the output. The SIMOSCEN signal enables the crystal oscillator
circuit.
The CGMXCLK signal is the output of the crystal oscillator circuit and runs at a rate equal to the crystal
frequency. CGMXCLK is then buffered to produce CGMRCLK, the PLL reference clock.
Freescale Semiconductor
Phase-Locked Loop with Output Frequency in Integer Multiples of the Crystal Reference
Programmable Hardware Voltage-Controlled Oscillator (VCO) for Low-Jitter Operation
Automatic Bandwidth Control Mode for Low-Jitter Operation
Automatic Frequency Lock Detector
CPU Interrupt on Entry or Exit from Locked Condition
Crystal oscillator circuit — The crystal oscillator circuit generates the constant crystal frequency
clock, CGMXCLK.
Phase-locked loop (PLL) — The PLL generates the programmable VCO frequency clock
CGMVCLK.
Base clock selector circuit — This software-controlled circuit selects either CGMXCLK divided by
two or the VCO clock, CGMVCLK, divided by two as the base clock, CGMOUT. The system clocks
are derived from CGMOUT.
shows the structure of the CGM.
MC68HC908AZ32A Data Sheet, Rev. 2
91

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