ad73460 Analog Devices, Inc., ad73460 Datasheet - Page 19

• Manufacturer Part Number: ad73460
• Description: Six-input Channel Analog Front End
• Manufacturer: Analog Devices, Inc.

Data Mode
Once the device has been configured by programming the cor-
rect settings to the various control registers, the device may exit
Program Mode and enter Data Mode. This is done by program-
ming the DATA/PGM (CRA:0) bit to 1 and MM (CRA:1) to 0.
Once the device is in Data Mode, the input data is ignored.
When the device is in normal Data Mode (i.e., mixed mode
disabled), it must receive a hardware reset to reprogram any of
the control register settings.
Mixed Program/Data Mode
This mode allows the user to send control words to the device
while receiving ADC words. This permits adaptive control of
the device whereby control of the input gains can be affected by
reprogramming the control registers. The standard data frame
remains 16 bits, but now the MSB is used as a flag bit to indicate
that the remaining 15 bits of the frame represent control
information. Mixed mode is enabled by setting the MM bit (CRA:1)
to 1 and the DATA/PGM bit (CRA:0) to 1. In the case where
control setting changes will be required during normal operation,
this mode allows the ability to load control information with the
slight inconvenience of formatting the data. Note that the output
samples from the ADC will also have the MSB set to zero to
indicate it is a data-word.
Channel Selection
The ADC channels of the AD73460 can be powered up or down
individually by programming the PUIx bit of registers CRD to
CRF. If the AD73460 is being used in Mixed Data/Control Mode,
individual channels may be powered up or down as the program
requires. In Data Mode, the number of channels selected while the
AD73460 was in Program Mode is fixed and cannot be altered
without resetting and reprogramming the AD73460. In all cases,
ADC Channel 1 must be powered up as the frame sync pulse
generated by this channel defines the start of a new sample interval.
INTERFACING
The AFE section SPORT (SPORT2) can be interfaced to either
SPORT0 or SPORT1 of the DSP section. Both serial input and
output data use an accompanying frame synchronization signal
that is active high one clock cycle before the start of the 16-bit
word or during the last bit of the previous word if transmission
is continuous. The serial clock (SCLK) is an output from the
AFE and is used to define the serial transfer rate to the DSP’s
Tx and Rx ports. Two primary configurations can be used: the
first is shown in Figure 8 where the DSP’s Tx data, Tx frame
sync, Rx data and Rx frame sync are connected to the AD73460’s
SDI, SDIFS, SDO, and SDOFS, respectively. This configuration,
referred to as indirectly coupled or nonframe sync loop-back,
has the effect of decoupling the transmission of input data from
the receipt of output data. When programming the DSP serial
port for this configuration, it is necessary to set the Rx frame
sync as an input to the DSP and the Tx frame sync as an output
generated by the DSP. This configuration is most useful when
operating in mixed mode, as the DSP has the ability to decide
how many words can be sent to the AFE(s). This means that full
control can be implemented over the device configuration in a given
sample interval. The second configuration (shown in Figure 9) has the
DSP’s Tx data and Rx data connected to the AFE’s SDI and SDO,
respectively, while the DSP’s Tx and Rx frame syncs are connected
to the AD73460’s SDIFS and SDOFS. In this configuration,
referred to as directly coupled or frame sync loop-back, the frame
sync signals are connected together and the input data to the AFE
REV. A
–19–
is forced to be synchronous with the output data from the AFE.
The DSP must be programmed so that both the Tx and Rx
frame syncs are inputs as the AFE’s SDOFS will be input to
both. This configuration guarantees that input and output events
occur simultaneously and is the simplest configuration for operation
in normal Data Mode. Note that when programming the AFE
in this configuration it is advisable to preload the transmit regis-
ter with the first control word to be sent before the AFE is taken
out of reset. This ensures that this word will be transmitted to
coincide with the first output word from the device(s).
Figure 8. Indirectly Coupled or Nonframe Sync Loop-Back
Configuration
Cascade Operation
The AD73460 has been designed to support cascading of an
external AFE from either SPORT0 or SPORT1. The SPORT2
interface protocol has been designed so that device addressing is
built into the packet of information sent to the device. This allows
the cascade to be formed with no extra hardware overhead for
control signals or addressing. A cascade can be formed in either
of the two modes previously discussed.
There may be some restrictions in cascade operation due to the
number of devices configured in the cascade and the serial clock
rate chosen. The formula below gives an indication of whether
the combination of sample rate, serial clock, and number of
devices can be successfully cascaded. This assumes a directly
coupled frame sync arrangement as shown in Figure 9 and does
not take any interrupt latency into account.
When using the indirectly coupled frame sync configuration in
cascaded operation, it is necessary to be aware of the restrictions
in sending control word data to all devices in the cascade. The
user should ensure that there is sufficient time for all the control
words to be sent between reading the last ADC sample and the
start of the next sample period.
Figure 9. Directly Coupled or Frame Sync Loop-Back
Configuration
SECTION
SECTION
DSP
DSP
f
1
S
≥
6
×
[((
TFS(0/1)
DT(0/1)
SCLK(0/1)
DR(0/1)
RFS(0/1)
TFS(0/1)
DT(0/1)
SCLK(0/1)
DR(0/1)
RFS(0/1)
Device Count
SCLK
SDOFS
SDIFS
−
SDIFS
SOFS
SCLK
SCLK
SDO
SDO
SDI
SDI
1
)
×
16
AD73460
)
SECTION
SECTION
+
AFE
AFE
17
]