ad73460 Analog Devices, Inc., ad73460 Datasheet - Page 20

• Manufacturer Part Number: ad73460
• Description: Six-input Channel Analog Front End
• Manufacturer: Analog Devices, Inc.

AD73460
In Cascade Mode, both devices must know the number of devices
in the cascade to be able to output data at the correct time.
Control Register A contains a 3-bit field (DC0–2) that is pro-
grammed by the DSP during the programming phase. The
default condition is that the field contains 000b, which is equiva-
lent to a single device in cascade (see Table XVI). However, for
cascade operation this field must contain a binary value that is
one less than the number of devices in the cascade. With a cascade,
each device takes a turn to send an ADC result to the DSP. For
example, in a cascade of two devices the data will be output as
Device 2-Channel 1, Device 1-Channel 1, Device 2-Channel 2,
Device 1-Channel 2 and so on. When the first device in the
cascade has transmitted its channel data, there is an additional
SCLK period during which the last device asserts its SDOFS as
it begins its transmission of the next channel. This will not
cause a problem for most DSPs as they count clock edges
after a frame sync and therefore the extra bit will be ignored.
When two devices are connected in cascade, there are also
restrictions concerning which ADC channels can be powered
up. In all cases the cascaded devices must all have the same
channels powered up (i.e., for a cascade requiring Channels 1
and 2 on Device 1 and Channel 5 on Device 2, Channels 1, 2,
and 5 must be powered up on both devices to ensure correct
operation).
DC2
0
0
0
0
1
1
1
1
Table XVI. Device Count Settings
DC1
0
0
1
1
0
0
1
1
DC0
0
1
0
1
0
1
0
1
GENERATORS
DAG 1
ADDRESS
ALU
DATA
ARITHMETIC UNITS
ADSP-2100 BASE
ARCHITECTURE
DAG 2
MAC
Cascade Length
1
2
3
4
5
6
7
8
Figure 10. Functional Block Diagram
SEQUENCER
PROGRAM
SHIFTER
ADC1
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
REF
ADC2
(OPTIONAL
SPORT 0
16K PM
SERIAL PORTS
POWER-DOWN
8K)
ANALOG FRONT END
CONTROL
MEMORY
–20–
ADC3
SERIAL PORT
SPORT 1
(OPTIONAL
SECTION
16K DM
SPORT 2
8K)
FUNCTIONAL DESCRIPTION—DSP
The AD73460 instruction set provides flexible data moves and
multifunction (one or two data moves with a computation) instruc-
tions. Every instruction can be executed in a single processor cycle.
The AD73460 assembly language uses an algebraic syntax for ease
of coding and readability. A comprehensive set of development
tools supports program development.
Figure 10 is an overall block diagram of the AD73460. The
processor contains three independent computational units: the
ALU, the multiplier/accumulator (MAC), and the shifter. The
computational units process 16-bit data directly and have provi-
sions to support multiprecision computations. The ALU performs
a standard set of arithmetic and logic operations; division primi-
tives are also supported. The MAC performs single-cycle
multiply, multiply/add, and multiply/subtract operations with 40
bits of accumulation. The shifter performs logical and arithmetic
shifts, normalization, denormalization, and derive exponent
operations.
The shifter can be used to efficiently implement numeric
format control including multiword and block floating-point
representations.
The internal result (R) bus connects the computational units so
that the output of any unit may be the input of any unit on the
next cycle.
A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these com-
putational units. The sequencer supports conditional jumps,
subroutine calls and returns in a single cycle. With internal loop
counters and loop stacks, the AD73460 executes looped code
with zero overhead; no explicit jump instructions are required to
maintain loops.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and
program memory). Each DAG maintains and updates four
address pointers. Whenever the pointer is used to access data
ADC4
TIMER
PROGRAMMABLE
FLAGS
ADC5
AND
I/O
ADC6
FULL MEMORY
CONTROLLER
EXTERNAL
EXTERNAL
BYTE DMA
ADDRESS
DATABUS
MODE
BUS
AD73460
REV. A