ad73460 Analog Devices, Inc., ad73460 Datasheet - Page 32

• Manufacturer Part Number: ad73460
• Description: Six-input Channel Analog Front End
• Manufacturer: Analog Devices, Inc.

AD73460
Figure 24 details the dc-coupled input circuits for single-ended
operation respectively.
Revision History
Location
10/02—Data Sheet changed from REV. 0 to REV. A.
Edits to Note 1 of SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Edits to TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 24. Example Circuit for Single-Ended Input
(DC Coupling)
VIN
100
0.047 F
0.1 F
REFOUT
REFCAP
VINNx
VINPx
3.50 MAX
2.15 NOM
14.00 BSC
TOP VIEW
A1
119-Lead Chip Scale Ball Grid Array (PBGA)
COPLANARITY
0.20
DETAIL A
REFERENCE
COMPLIANT TO JEDEC STANDARDS MS-028AA
VOLTAGE
Dimensions shown in millimeters
22.00
OUTLINE DIMENSIONS
BSC
0.70
0.60
0.50
SEATING
(B-119)
REF
0.84
PLANE
–32–
BSC
BOTTOM
1.27
VIEW
DETAIL A
Digital Interface
As there are a number of variations of sample rate and clock speeds
that can be used with the AD73460 in a particular application,
it is important to select the best combination to achieve the
desired performance. High speed serial clocks will read the data
from the AD73460 in a shorter time, giving more time for
processing at the expense of injecting some digital noise into the
circuit. Digital noise can also be reduced by connecting resistors
(typ <50 Ω) in series with the digital input and output lines.
The noise can be minimized by good grounding and layout.
Typically the best performance is achieved by selecting the slowest
sample rate and SCLK frequency for the required application, as
this will produce the least amount of digital noise.
3.19
REF
7 6 5 4 3 2 1
7.62 BSC
0.90
0.75
0.60
BALL DIAMETER
1.27
BSC
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
20.32
BSC
2.50
0.10
2.50 MAX
REV. A
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