ad73460 Analog Devices, Inc., ad73460 Datasheet - Page 28

• Manufacturer Part Number: ad73460
• Description: Six-input Channel Analog Front End
• Manufacturer: Analog Devices, Inc.

AD73460
DSP with only one DSP cycle per word overhead. The IDMA
port cannot be used, however, to write to the DSP’s memory-
mapped control registers. A typical IDMA transfer process is
described as follows:
1. Host starts IDMA transfer.
2. Host checks IACK control line to see if the DSP is busy.
3. Host uses IS and IAL control lines to latch either the DMA
4. Host uses IS and IRD (or IWR) to read (or write) DSP internal
5. Host checks IACK line to see if the DSP has completed the
6. Host ends IDMA transfer.
The IDMA port has a 16-bit multiplexed address and databus
and supports 24-bit program memory. The IDMA port is
completely asynchronous and can be written to while the
AD73460 is operating at full speed.
The DSP memory address is latched and then automatically
incremented after each IDMA transaction. An external device
can therefore access a block of sequentially addressed memory
by specifying only the starting address of the block. This increases
throughput as the address does not have to be sent for each
memory access.
IDMA Port access occurs in two phases. The first is the IDMA
Address Latch cycle. When the acknowledge is asserted, a
14-bit address and 1-bit destination type can be driven onto the
bus by an external device. The address specifies an on-chip
memory location; the destination type specifies whether it is a
DM or PM access. The falling edge of the address latch signal
latches this value into the IDMAA register.
Once the address is stored, data can either be read from or
written to the AD73460’s on-chip memory. Asserting the select
line (IS) and the appropriate read or write line (IRD and IWR
respectively) signals the AD73460 that a particular transaction
is required. In either case, there is a one-processor-cycle delay
for synchronization. The memory access consumes one addi-
tional processor cycle.
Once an access has occurred, the latched address is automati-
cally incremented and another access can occur.
Through the IDMAA register, the DSP can also specify the
starting address and data format for DMA operation. Asserting
the IDMA port select (IS) and address latch enable (IAL) directs
the AD73460 to write the address onto the IAD0–14 bus into
the IDMA Control Register. If IAD[15] is set to 0, IDMA
latches the address. The IDMAA register, shown below, is
memory mapped at address DM (0x3FE0). Note that the
latched address (IDMAA) cannot be read back by the host. The
IDMA OVLAY register is memory mapped at address DM
(0x3FE7). See Figure 17 for more information on IDMA and
DMA memory maps.
starting address (IDMAA) or the PM/DM OVLAY selection
into the DSP’s IDMA control registers.
IAD[15] must be set to 0.
memory (PM or DM).
previous IDMA operation.
–28–
Bootstrap Loading (Booting)
The AD73460 has two mechanisms to allow automatic loading
of the internal program memory after reset. The method for
booting after reset is controlled by the Mode A, B, and C con-
figuration bits.
When the mode pins specify BDMA booting, the AD73460
initiates a BDMA boot sequence when reset is released.
The BDMA interface is set up during reset to the following
defaults when BDMA booting is specified: the BDIR, BMPAGE,
BIAD, and BEAD registers are set to 0, the BTYPE register is
set to 0 to specify program memory 24-bit words, and the
BWCOUNT register is set to 32. This causes 32 words of on-
chip program memory to be loaded from byte memory. These
32 words are used to set up the BDMA to load in the remaining
program code. The BCR bit is also set to 1, which causes pro-
gram execution to be held off until all 32 words are loaded into
on-chip program memory. Execution then begins at address 0.
The ADSP-2100 Family Development Software (Revision 5.02
and later) fully supports the BDMA booting feature and can
generate byte memory space compatible boot code.
The IDLE instruction can also be used to allow the processor to
hold off execution while booting continues through the BDMA
interface. For BDMA accesses while in Host Mode, the addresses
to boot memory must be constructed externally to the AD73460.
The only memory address bit provided by the processor is A0.
IDMA Port Booting
The AD73460 can also boot programs through its Internal
DMA port. If Mode C = 1, Mode B = 0, and Mode A = 1, the
AD73460 boots from the IDMA port. IDMA feature can load
as much on-chip memory as desired. Program execution is held
off until on-chip program memory location 0 is written to.
Bus Request and Bus Grant (Full Memory Mode)
The AD73460 can relinquish control of the data and address
buses to an external device. When the external device requires
access to memory, it asserts the bus request (BR) signal. If the
AD73460 is not performing an external memory access, it
responds to the active BR input in the following processor
cycle by:
• three-stating the data and address buses and the PMS, DMS,
• asserting the bus grant (BG) signal, and
• halting program execution.
If Go Mode is enabled, the AD73460 will not halt program
execution until it encounters an instruction that requires an
external memory access.
BMS, CMS, IOMS, RD, WR output drivers,
15 14 13 12 11 10
U
Figure 17. IDMA Control/OVLAY Registers
IDMAD
DESTINATION MEMORY TYPE:
IDMA CONTROL (U = UNDEFINED AT RESET)
U
0 = PM
1 = DM
U
U
U
9
U
IDMAA ADDRESS
8
U
U
7
6
U
5
U
4
U
3
U
U
2
1
U
0
U
DM(0x3FE0)
REV. A