mt48lc16m8a2tg-75-it Micron Semiconductor Products, mt48lc16m8a2tg-75-it Datasheet - Page 44

• Manufacturer Part Number: mt48lc16m8a2tg-75-it
• Description: 128mb X4, X8, X16 Sdram
• Manufacturer: Micron Semiconductor Products

PDF: 09005aef8091e66d/Source: 09005aef8091e625
128MSDRAM_2.fm - Rev. M 10/07 EN
10. For a READ without auto precharge interrupted by a READ (with or without auto pre-
11. For a READ without auto precharge interrupted by a WRITE (with or without auto pre-
12. For a WRITE without auto precharge interrupted by a READ (with or without auto pre-
13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto pre-
14. For a READ with auto precharge interrupted by a READ (with or without auto precharge),
15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge),
16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge),
17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge),
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs to bank m listed in the Command (Action) column include READs or
8. Concurrent auto precharge: Bank n will initiate the auto precharge command when its
9. Burst in bank n continues as initiated.
represented by the current state only.
WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled.
burst has been interrupted by bank m’s burst.
charge), the READ to bank m will interrupt the READ on bank n, CL later (Figure 13 on
page 26).
charge), the WRITE to bank m will interrupt the READ on bank n when registered (Figure 15
on page 28 and Figure 16 on page 28). DQM should be used 1 clock prior to the WRITE com-
mand to prevent bus contention.
charge), the READ to bank m will interrupt the WRITE on bank n when registered (Figure 23
on page 33), with the data-out appearing CL later. The last valid WRITE to bank n will be
data-in registered 1 clock prior to the READ to bank m.
charge), the WRITE to bank m will interrupt the WRITE on bank n when registered
(Figure 21 on page 32). The last valid WRITE to bank n will be data-in registered 1 clock
prior to the READ to bank m.
the READ to bank m will interrupt the READ on bank n, CL later. The precharge to bank n
will begin when the READ to bank m is registered (Figure 30 on page 38).
the WRITE to bank m will interrupt the READ on bank n when registered. DQM should be
used 2 clocks prior to the WRITE command to prevent bus contention. The precharge to
bank n will begin when the WRITE to bank m is registered (Figure 31 on page 38).
the READ to bank m will interrupt the WRITE on bank n when registered, with the data-out
appearing CL later. The precharge to bank n will begin after
when the READ to bank m is registered. The last valid WRITE to bank n will be data-in regis-
tered one clock prior to the READ to bank m (Figure 32 on page 39).
the WRITE to bank m will interrupt the WRITE on bank n when registered. The precharge to
bank n will begin after
tered. The last valid WRITE to bank n will be data registered 1 clock prior to the WRITE to
bank m (Figure 33 on page 39).
t
WR is met, where
44
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
WR begins when the WRITE to bank m is regis-
128Mb: x4, x8, x16 SDRAM
t
WR is met, where
©1999 Micron Technology, Inc. All rights reserved.
Operation
t
WR begins