mt48lc16m8a2tg-75-it Micron Semiconductor Products, mt48lc16m8a2tg-75-it Datasheet - Page 52

• Manufacturer Part Number: mt48lc16m8a2tg-75-it
• Description: 128mb X4, X8, X16 Sdram
• Manufacturer: Micron Semiconductor Products

PDF: 09005aef8091e66d/Source: 09005aef8091e625
128MSDRAM_2.fm - Rev. M 10/07 EN
22. V
23. The clock frequency must remain constant (stable clock is defined as a signal cycling
24. Auto precharge mode only. The precharge timing budget (
25. Precharge mode only.
26. JEDEC and PC100 specify 3 clocks.
27.
28. Parameter guaranteed by design.
29. PC100 specifies a maximum of 4pF.
30. PC100 specifies a maximum of 5pF.
31. PC100 specifies a maximum of 6.5pF.
32. For -75, CL = 3 and
33. CKE is HIGH during refresh command period
34. PC133 specifies a minimum of 2.5pF.
35. PC133 specifies a minimum of 2.5pF.
36. PC133 specifies a minimum of 3.0pF.
cannot be greater than one-third of the cycle rate. V
a pulse width
within timing constraints specified for the clock pin) during access or precharge
states (READ, WRITE, including
used to reduce the data rate.
for -7E, and 7.5ns for -75 after the first clock delay, after the last WRITE is executed.
t
6ns.
limit is actually a nominal value and does not result in a fail value.
AC for -75/-7E at CL = 3 with no load is 4.6ns and is guaranteed by design.
IH
overshoot: V
≤
3ns.
IH
(MAX) = V
t
CK = 7.5ns; for -7E, CL = 2 and
52
DD
Q + 2V for a pulse width
t
WR, and PRECHARGE commands). CKE may be
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RFC (MIN) else CKE is LOW. The I
t
128Mb: x4, x8, x16 SDRAM
CK = 7.5ns, and CL = 3 and
IL
undershoot: V
≤
3ns, and the pulse width
t
RP) begins 6ns for -6A, 7ns
©1999 Micron Technology, Inc. All rights reserved.
IL
(MIN) = –2V for
Notes
t
CK =
DD
6