mt48h4m16lf Micron Semiconductor Products, mt48h4m16lf Datasheet - Page 29

• Manufacturer Part Number: mt48h4m16lf
• Description: 64mb 4 Meg X 16 Mobile Sdram Features
• Manufacturer: Micron Semiconductor Products

Figure 24:
Deep Power-Down
Clock Suspend
PDF: 09005aef8237ed98/Source: 09005aef8237ed68
64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. C 10/07 EN
Power-Down
Deep power-down mode is a maximum power savings feature achieved by shutting off
the power to the entire memory array of the device. Data on the memory array will not
be retained after deep power-down mode is executed. Deep power-down mode is
entered by having all banks idle then CS# and WE# held LOW with RAS# and CAS# HIGH
at the rising edge of the clock, while CKE is LOW. CKE must be held LOW during deep
power-down.
To exit deep power-down mode, CKE must be asserted HIGH. Upon exit of deep power-
down mode, a full Mobile SDRAM initialization sequence is required.
The clock suspend mode occurs when a column access/burst is in progress and CKE is
registered LOW. In the clock suspend mode, the internal clock is deactivated, “freezing”
the synchronous logic.
For each positive clock edge on which CKE is sampled LOW, the next internal positive
clock edge is suspended. Any command or data present on the input pins at the time of a
suspended internal clock edge is ignored; any data present on the DQ pins remains
driven; and burst counters are not incremented, as long as the clock is suspended. (See
examples in Figure 25 on page 30 and Figure 26 on page 30.)
Clock suspend mode is exited by registering CKE HIGH; the internal clock and related
operation will resume on the subsequent positive clock edge.
Command
CKE
CLK
All banks idle
Enter power-down mode
t CKS
NOP
Input buffers gated off
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Exit power-down mode
Micron Technology, Inc., reserves the right to change products or specifications without notice.
64Mb: 4 Meg x 16 Mobile SDRAM
> t CKS
NOP
©2006 Micron Technology, Inc. All rights reserved.
ACTIVE
t RCD
t RAS
t RC
Operations