mt4lc4m4e8tg-6-s Micron Semiconductor Products, mt4lc4m4e8tg-6-s Datasheet - Page 3

• Manufacturer Part Number: mt4lc4m4e8tg-6-s
• Description: 16mb Edo Mt4lc4m4e8dj-5
• Manufacturer: Micron Semiconductor Products

EDO PAGE MODE (continued)
tively, pulsing WE# to the idle banks during CAS# HIGH
time will also High-Z the outputs. Independent of OE#
control, the outputs will disable after
enced from the rising edge of RAS# or CAS#, whichever
occurs last.
DRAM REFRESH
and executing any RAS# cycle (READ, WRITE) or RAS#
REFRESH cycle (RAS#-ONLY, CBR or HIDDEN) so that all
combinations of RAS# addresses (2,048 for 2K and 4,096 for
4K) are executed within
quence. The CBR and SELF REFRESH cycles will invoke the
internal refresh counter for automatic RAS# addressing.
version. The self refresh feature is initiated by performing
a CBR REFRESH cycle and holding RAS# LOW for the
specified
of a fully static, low-power data retention mode or a dy-
namic refresh mode at the extended refresh period of 128ms,
4 Meg x 4 EDO DRAM
D47.p65 – Rev. 6/98
ADDR
RAS#
CAS#
WE#
OE#
DQ
Preserve correct memory cell data by maintaining power
An optional self refresh mode is also available on the “S”
V
V
IOH
IOL
V
V
V
V
V
V
V
V
V
V
IH
IL
IH
IL
IH
IL
IH
IL
IH
IL
t
RASS. The “S” option allows the user the choice
ROW
OPEN
t
REF (MAX), regardless of se-
COLUMN (A)
t
OFF, which is refer-
VALID DATA (A)
The DQs go to High-Z if WE# falls and, if
will remain High-Z until CAS# goes LOW with
WE# HIGH (i.e., until a READ cycle is initiated).
WE# CONTROL OF DQs
t
WHZ
t WPZ
Figure 2
3
or 31.25µs per row for a 4K refresh and 62.5µs per row for
a 2K refresh, when using a distributed CBR REFRESH. This
refresh rate can be applied during normal operation, as well
as during a standby or battery backup mode.
HIGH for a minimum time of
completion of any internal refresh cycles that may be in
process at the time of the RAS# LOW-to-HIGH transition.
If the DRAM controller uses a distributed refresh se-
quence, a burst refresh is not required upon exiting
self refresh. However, if the DRAM controller utilizes a
RAS#-ONLY or burst refresh sequence, all rows must be
refreshed within the average internal refresh rate, prior to
the resumption of normal operation.
STANDBY
cycle and decreases chip current to a reduced standby level.
The chip is preconditioned for the next cycle during the
RAS# HIGH time.
COLUMN (B)
The self refresh mode is terminated by driving RAS#
Returning RAS# and CAS# HIGH terminates a memory
t
WPZ is met,
Micron Technology, Inc., reserves the right to change products or specifications without notice.
VALID DATA (B)
WE# may be used to disable the DQs to prepare
for input data in an EARLY WRITE cycle. The DQs
will remain High-Z until CAS# goes LOW with
WE# HIGH (i.e., until a READ cycle is initiated).
t
WHZ
t
RPS. This delay allows for the
COLUMN (C)
INPUT DATA (C)
EDO DRAM
4 MEG x 4
1998, Micron Technology, Inc.
DON’T CARE
UNDEFINED
COLUMN (D)