ics9248-136 Integrated Device Technology, ics9248-136 Datasheet - Page 2

• Manufacturer Part Number: ics9248-136
• Description: Frequency Generator & Integrated Buffers For K7 Processor
• Manufacturer: Integrated Device Technology

Advance Information
Pin Configuration
Third party brands and names are the property of their respective owners.
ICS9248-136
26, 33, 34, 36, 37,
4, 14, 18, 19, 29,
PIN NUMBER
1, 7, 15, 22, 25,
13, 12, 11, 10
38, 40, 41, 42
35, 43, 48
32, 39, 44
17, 16
45, 47
20
21
23
24
27
28
30
31
46
2
3
5
6
8
9
SDRAM (12, 7:0)
SDRAM_STOP#
CPUCLKT (1:0)
AGPCLK (1:0)
PCICLK (4:1)
CPU_STOP#
CPUCLKC0
PIN NAME
PCI_STOP#
PCICLK_F
SDRAM 11
SDRAM 10
24_48M Hz
SDRAM9
SDRAM8
PCICLK0
AGPSEL
SDATA
48MHz
M ODE
SCLK
REF1
REF0
VDD
GND
PD#
FS3
FS1
FS2
FS0
X1
X2
TYPE
PWR
PWR
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
I/O
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
3.3V Power supply for SDRAM output buffers, PCI output buffers,
reference output buffers and 48MHz output
AGP frequency select pin.
14.318 MHz reference clock.
Frequency select pin.
14.318 MHz reference clock.
Ground pin for 3V outputs.
Crystal input,nominally 14.318M Hz.
Crystal output, nominally 14.318MHz.
Frequency select pin.
PCI clock output, not affected by PCI_STOP#
Frequency select pin.
PCI clock output.
PCI clock outputs.
AGP outputs defined as 2X PCI. These may not be stopped.
Frequency select pin.
48M Hz output clock
Pin 27, 28, 30, & 31 function select pin
0=Desktop 1=M obile mode
Clock output for super I/O/USB default is 24M Hz
Data pin for I
Clock pin of I
Stops all CPUCLKs clocks at logic 0 level, when input low
(when M ODE active).
SDRAM clock output
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level,
when input low (when M ODE active).
SDRAM clock output
Stops all SDRAM clocks at logic 0 level, when input low
(when M ODE active)
SDRAM clock output
Asynchronous active low input pin used to power down the device into a low
power state. The internal clocks are disabled and the VCO and the crystal are
stopped. The latency of the power down will not be greater than 3ms. (when
M ODE active)
SDRAM clock output
SDRAM clock outputs
Complementory"" clocks of differential pair CPU outputs. These clocks are
180° out of phase with SDRAM clocks. These open drain outputs need an
external 1.5V pull-up.
"True" clocks of differential pair CPU outputs. These clocks are in phase with
SDRAM clocks. These open drain outputs need an external 1.5V pull-up.
2
2
2
C circuitry 5V tolerant
C circuitry 5V tolerant
DESCRIPTION