ics9248-165 Integrated Device Technology, ics9248-165 Datasheet - Page 7

• Manufacturer Part Number: ics9248-165
• Description: Frequency Generator & Integrated Buffers For Celeron & Pii/iii
• Manufacturer: Integrated Device Technology

high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU, IOAPIC, SDRAM clocks are disabled. The
CPU clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse.
CPU clock on latency is less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
CLK_STOP# Timing Diagram
CLK_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU, IOAPIC, SDRAM clocks for low
power operation. CLK_STOP# is synchronized by the ICS9248-165. The minimum that the CPU clock is enabled (CLK_STOP#
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Notes:
1. All timing is referenced to the internal CPU clock.
2. CLK_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized
3. IOAPIC output is Stopped Glitch Free by CLK_STOP# going low.
4. SDRAM-F output is controlled by Buffer in signal, not affected by the ICS9248-165
5. All other clocks continue to run undisturbed.
to the CPU clocks inside the ICS9248-165.
CLK_STOP# signal. SDRAM's are controlled as shown.
PCI_STOP# (High)
CLK_STOP#
CPUCLK _F
INTERNAL
SDRAM_F
CPUCLK
CPUCLK
PCICLK
SDRAM
IOAPIC
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ICS9248-165