pck2010 NXP Semiconductors, pck2010 Datasheet

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pck2010

Manufacturer Part Number
pck2010
Description
Ck98 100/133mhz Spread Spectrum System Clock Generator
Manufacturer
NXP Semiconductors
Datasheet

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Part Number
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Quantity
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Part Number:
pck2010DL
Manufacturer:
PHILIPS
Quantity:
310
Part Number:
pck2010R
Manufacturer:
PHILIPS
Quantity:
1 245
Philips
Semiconductors
Preliminary specification
PCK2010
CK98 (100/133MHz) Spread Spectrum
System Clock Generator
INTEGRATED CIRCUITS
1999 Mar 01

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pck2010 Summary of contents

Page 1

... PCK2010 CK98 (100/133MHz) Spread Spectrum System Clock Generator Preliminary specification Philips Semiconductors INTEGRATED CIRCUITS 1999 Mar 01 ...

Page 2

... DESCRIPTION The PCK2010 is a clock synthesizer/driver chip for a PentiumII and other similar processors. The PCK2010 has four CPU clock outputs at 2.5V, two CPUDIV2 clock outputs running at ½ CPU clock frequency (66MHz or 50MHz depending on the state of SEL133/100) and four 3V66 clocks running at 66MHz ...

Page 3

... SEL133/100. 2.5V clock outputs running divide synchronous with the CPU clock IOAPIC [0–2] frequency. Fixed 16.67 MHz limit. V 3.3V power supply. DD3V V Ground SS V 2.5V power supply DD25V DD25V pins being common. 3 Preliminary specification PCK2010 FUNCTION pins tied to a 2.5V supply, all remaining V pins DD ...

Page 4

... LOGIC PWRDWN X LOGIC PWRDWN USBPLL X LOGIC STOP SYSPLL X STOP X PWRDWN X LOGIC PWRDWN X PCICLK_F (33MHz) LOGIC STOP X PWRDWN X APIC [0–2] (½ PCI) LOGIC 4 Preliminary specification PCK2010 REF [0–1](14.318 MHz) 48MHz CPUCLK [0–3] 3V66 [0–3] (66MHz) CPUDIV2 [0–1] PCICLK [1–7] (33MHz) SW00353 ...

Page 5

... HI-Z 50MHz 66MHz 33MHz 48MHz TCLK/4 TCLK/4 TCLK/8 TCLK/2 N/A N/A N/A N/A 66MHz 66MHz 33MHz HI-Z 66MHz 66MHz 33MHz 48MHz ACTUAL FREQUENCY (MHz) 48.0 48.008 5 Preliminary specification PCK2010 SW00403 REF IOAPIC NOTES HI-Z HI-Z 1 N/A N/A 2 14.318MHz 16.67MHz 3 14.318MHz 16.67MHz TCLK TCLK/ N/A N/A 2 14.318MHz 16.67MHz 3 14.318MHz 16.67MHz ...

Page 6

... I Note 2 V > < Note For temperature range: –40 to +125 C above +55 C derate linearly with 11.3mW/K 6 Preliminary specification PCK2010 PCI PCIF REF 48MHz OSC VCOs LOW LOW LOW OFF OFF LOW ...

Page 7

... MAXIMUM 3.3V SUPPLY CONSUMPTION = 2.625V MAXIMUM DISCRETE CAP LOADS, V DD25V OR V ALL STATIC INPUTS = V DD3V SS 100 A 75mA 90mA 7 Preliminary specification PCK2010 LIMITS UNIT UNIT MIN MAX 3.135 3.465 V 2.375 2.625 ...

Page 8

... Outputs loaded 133MHz mode Outputs loaded 3.465 All static inputs GND DD 100MHz mode Output loaded 2.625 133MHz mode Output loaded All static inputs GND DD 8 Preliminary specification PCK2010 LIMITS +70 C UNIT amb MIN TYP MAX 2 0 – 0.3 0.8 ...

Page 9

... MODE 100MHz MODE MIN MAX MIN MAX 30.0 n/a 30.0 n/a 12.0 n/a 12.0 n/a 12.0 n/a 12.0 n/a 0.5 2.0 0.5 2.0 0.5 2.0 0.5 2.0 500 500 500 500 9 Preliminary specification PCK2010 UNIT UNIT NOTES NOTES UNIT NOTES UNIT NOTES ...

Page 10

... MODE MIN MAX 15.0 16.0 5.25 n/a 5.05 n/a 0.4 1.6 0.4 1.6 500 45 55 250 TEST CONDITIONS PARAMETER Determined by PLL divider ratio (48.008 – 48)/48 Duty Cycle 133MHz MIN 10 Preliminary specification PCK2010 LIMITS +70 C amb UNIT UNIT NOTES NOTES 100MHz MODE MIN MAX 60.0 64 25.5 n 25.3 n 0.4 1 ...

Page 11

... The average period over any 1 s period of time must be greater than the minimum specified period. 10. Calculated at minimum edge-rate (1V/ns) to guarantee 45/55% duty-cycle. Pulse width is required to be wider at faster edge-rate to ensure duty-cycle specification is met. 11. Output (see Figure 3 for measure points). PCK2010 SPREAD SPECTRUM FUNCTION TABLE SPREAD# SEL133/100# SEL1 ...

Page 12

... Figure 3. CPU to IOAPIC offset V DDQ3 V SS 2.0 2.5V CLOCKING 1.25 INTERFACE 0.4 V DDQ3 V SS 2.4 3.3V CLOCKING 1.5 INTERFACE 0.4 (TTL) SW00356 Figure 4. 2.5V/3.3V clock waveforms 12 Preliminary specification PCK2010 Active Inactive Active Active Active Inactive Active V DDQ2 1.25V DDQ2 1.25V V SS CPUCLK leads IOAPIC SW00357 T HKP DUTY CYCLE T HKH ...

Page 13

... OUTPUT LOW-to-OFF POINTS OFF-to-LOW PHZ V OH OUTPUT HIGH-to-OFF OFF-to-HIGH SYSTEM MEASUREMENT V SS POINTS outputs enabled SW00243 Figure 6. 3-State enable and disable times 13 Preliminary specification PCK2010 t PZL PZH outputs outputs enabled disabled SW00454 ...

Page 14

... V O D.U. TEST Open PLH PHL t /t 2<V PLZ PZL PHZ PZH DEPENDS ON THE OUTPUT DDQ2 DDQ3 Figure 7. Load circuitry for switching times Figure 8. Power Management 14 Preliminary specification PCK2010 S 1 2<V DD Open V SS 500 500 SW00238 SW00244 ...

Page 15

... Philips Semiconductors CK98 (100/133MHz) Spread Spectrum System Clock Generator SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm 1999 Mar 01 15 Preliminary specification PCK2010 SOT371-1 ...

Page 16

... Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Philips Semiconductors yyyy mmm dd [1] © Copyright Philips Electronics North America Corporation 1998 print code Document order number: 16 Preliminary specification PCK2010 All rights reserved. Printed in U.S.A. Date of release: 05-96 9397-750-04955 ...

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