pckv857 NXP Semiconductors, pckv857 Datasheet - Page 2

• Manufacturer Part Number: pckv857
• Description: 70-190 Mhz Differential 1 10 Clock Driver
• Manufacturer: NXP Semiconductors

1. 48 balls are connected, 8 balls are no-connects.
FEATURES
DESCRIPTION
The PCKV857 is a high-performance, low-skew, low-jitter zero delay
buffer designed for 2.5 V V
differential data input and output levels.
The PCKV857 is a zero delay buffer that distributes a differential
clock input pair (CLK, CLK) to ten differential pairs of clock outputs
(Y[0:9], Y[0:9]) and one differential pair feedback clock outputs
(FB
inputs (CLK, CLK), the feedback clocks (FB
power input (AV
phase and frequency with CLK. When PWRDWN is low, all outputs
are disabled to high impedance state (3-State), and the PLL is shut
down (low power mode). The device also enters the low power
mode when the input frequency falls below 20 MHz. An input
frequency detection circuit will detect the low frequency condition
and after applying a > 20 MHz input signal, the detection circuit
turns on the PLL again and enables the outputs.
When AV
purposes. The PCKV857 is also able to track spread spectrum
clocking for reduced EMI.
The PCKV857 is characterized for operation from 0 to +70 C.
ORDERING INFORMATION
NOTE:
Philips Semiconductors
2002 Sep 13
ESD classification testing is done to JEDEC Standard JESD22.
Protection exceeds 2000 V to HBM per method A114.
Latch-up testing is done to JEDEC Standard JESD78 which
exceeds 100 mA
Optimized for clock distribution in DDR (Double Data Rate)
SDRAM applications as per JEDEC specifications
1-to-10 differential clock distribution
Very low skew ( 100 ps) and jitter ( 100 ps)
Operation from 2.2 V to 2.7 V AV
SSTL_2 interface clock inputs and outputs
CMOS control signal input
Test mode enables buffers while disabling PLL
Low current power-down mode
Tolerant of Spread Spectrum input clock
Full DDR solution provided when used with SSTL16877 or
SSTV16857
Designed for DDR 200 and 266 DIMM applications
Available in TSSOP-48, TVSOP-48, and VFBGA56
(8 no connects) packages
70–190 MHz differential 1:10 clock driver
48-Pin Plastic TSSOP (TVSOP)
OUT
56-ball Plastic VFBGA
, FB
48-Pin Plastic TSSOP
DD
OUT
is grounded, the PLL is turned off and bypassed for test
PACKAGES
) . The clock outputs are controlled by the clock
DD
). When PWRDWN is high, the outputs switch in
DD
1
and 2.5 V AV
DD
and 2.3 V to 2.7 V V
DD
IN
TEMPERATURE RANGE
, FB
operation and
IN
0 to +70 C
0 to +70 C
0 to +70 C
), and the analog
DD
2
PIN CONFIGURATION
ORDER CODE
PCKV857DGG
PCKV857DGV
PCKV857EV
AGND
V
V
V
V
V
AV
GND
GND
GND
GND
GND
CLK
CLK
DDQ
DDQ
DDQ
DDQ
DDQ
Y
Y
Y
Y
Y
Y
DD
Y
Y
Y
Y
0
0
1
1
2
2
3
3
4
4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
7
1
2
3
4
5
6
8
9
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
GND
Y
Y
V
Y
Y
GND
GND
Y
Y
V
PWRDWN
FB
FB
V
FB
FB
GND
Y
Y
V
Y
Y
GND
DRAWING NUMBER
5
5
DDQ
6
6
7
7
DDQ
DDQ
8
8
DDQ
9
9
SW00691
IN
IN
OUT
OUT
SOT362-1
SOT480-1
SOT702-1
PCKV857
Product data