w83195bg-912 Winbond Electronics Corp America, w83195bg-912 Datasheet - Page 16

• Manufacturer Part Number: w83195bg-912
• Description: Clock For Via Chipsets
• Manufacturer: Winbond Electronics Corp America

7.8
7.9
7.10 Register 9: Divider Ratio (Default: 02h)
BIT
9IT
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Register 7: M/N Program (Default: 2Fh)
Register 8: Spread Spectrum Program (Default: 1Fh)
IN to FBOUT<2>
IN to FBOUT<1>
IN to FBOUT<0>
SP_DOWN [3]
SP_DOWN [2]
SP_DOWN [1]
SP_DOWN [0]
SEL_CLKSTOP
N_DIV [7]
N_DIV [6]
N_DIV [5]
N_DIV [4]
N_DIV [3]
N_DIV [2]
N_DIV [1]
N_DIV [0]
SP_UP [3]
SP_UP [2]
SP_UP [1]
SP_UP [0]
NAME
NAME
Name
N<9>
DS2
DS1
DS0
CLOCK GEN. FOR VIA P4/KT SERIES CHIPSET
PWD
0
0
1
0
1
1
1
1
PWD
0
0
0
1
1
1
1
1
Programmable N divisor value bit 7 ~0.
The bit 8 is defined in Register 6, Bit 7.
The bit 9 is defined in Register 9, Bit 7.
PWD
Spread Spectrum Up Counter bit 3 ~ bit 0.
Spread Spectrum Down Counter bit 3 ~ bit 0
2’s complement representation.
Ex: 1 -> 1111; 2 -> 1110; 7 -> 1001; 8 -> 1000
0
0
0
0
0
0
1
0
Function Description
Programmable N divisor value bit 9
Refer to Table-2
BUF_IN to FBOUT skew control.
300ps/per stage
Define the CPU/AGP/PCI divider ratio
Refer to Table-3
- 12 -
FUNCTION DESCRIPTION
FUNCTION DESCRIPTION
W83195BG-912