w83195bg-912 Winbond Electronics Corp America, w83195bg-912 Datasheet - Page 3

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w83195bg-912

Manufacturer Part Number
w83195bg-912
Description
Clock For Via Chipsets
Manufacturer
Winbond Electronics Corp America
Datasheet

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
W83195BG-912
Manufacturer:
WINBOND/华邦
Quantity:
20 000
Table of Content-
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GENERAL DESCRIPTION ......................................................................................................... 1
PRODUCT FEATURES .............................................................................................................. 1
PIN CONFIGURATION ............................................................................................................... 2
BLOCK DIAGRAM ...................................................................................................................... 3
PIN DESCRIPTION..................................................................................................................... 4
FREQUENCY SELECTION BY HARDWARE OR SOFTWARE ................................................ 8
I
5.1
5.2
5.3
5.4
5.5
5.6
5.7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
7.14
7.15
7.16
7.17
7.18
7.19
7.20
2
C CONTROL AND STATUS REGISTERS............................................................................... 9
Crystal I/O.................................................................................................................................4
CPU, AGP, PCI Clock Outputs................................................................................................4
Fixed Frequency Outputs.........................................................................................................5
DRAM Buffer ............................................................................................................................6
I2C Control Interface ................................................................................................................6
Output Control Pins ..................................................................................................................6
Power an GND Pins .................................................................................................................7
Register 0: Frequency Select (Default =08h) ..........................................................................9
Register 1: SRC/CPU Clock (1 = Enable, 0 = Disable) (Default: A9h)...................................9
Register 2: PCI Clock (1 = Enable, 0 = Disable) (Default: FEh) ...........................................10
Register 3: REF, 24_48,48,AGP Clock (1 = Enable, 0 = Disable) (Default: F7h)................10
Register 4: Watchdog Control (Default: 81h) ........................................................................10
Register 5: Watch dog timer (Default: 08h) ...........................................................................11
Register 6: M/N Program (Default: 8Bh) ...............................................................................11
Register 7: M/N Program (Default: 2Fh)................................................................................12
Register 8: Spread Spectrum Program (Default: 1Fh)..........................................................12
Register 9: Divider Ratio (Default: 02h).................................................................................12
Register 10: Control (Default: 0Ah)........................................................................................13
Register 11: Control (Default: X7h)........................................................................................14
Register 12: Control (Default: 3Ch) .......................................................................................14
Register 13: Control (Default: 24h) ........................................................................................15
Register 14: Control (Default: 5Xh)........................................................................................15
Register 15: Slew Rate Control (Default: 55h) ......................................................................15
Register 16: DRAM Buffer Control (1 = Enable, 0 = Disable) (Default: 7Fh).......................16
Register 17: Slew Rate Control (Default: CFh) .....................................................................16
Register 18: M/N Time & Type Control (Default: 5Bh)..........................................................17
Register 19: Reserved ...........................................................................................................17
CLOCK GEN. FOR VIA P4/KT SERIES CHIPSET
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W83195BG-912

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