adf4153 Analog Devices, Inc., adf4153 Datasheet - Page 8

• Manufacturer Part Number: adf4153
• Description: Fractional-n Frequency Synthesizer
• Manufacturer: Analog Devices, Inc.

ADF4153
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 11. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REF
on power-down.
RF INPUT STAGE
The RF input stage is shown in Figure 12. It is followed by a
2-stage limiting amplifier to generate the current-mode logic
(CML) clock levels needed for the prescaler.
RF
RF
IN
IN
A
B
REF
IN
GENERATOR
NC
POWER-DOWN
Figure 11. Reference Input Stage
SW1
CONTROL
BIAS
Figure 12. RF Input Stage
NO
NC
SW3
SW2
2kΩ
100kΩ
1.6V
BUFFER
2kΩ
TO R COUNTER
AGND
AV
DD
IN
pin
Rev. B | Page 8 of 24
RF INT DIVIDER
The RF INT CMOS counter allows a division ratio in the PLL
feedback counter. Division ratios from 31 to 511 are allowed.
INT, FRAC, MOD, AND R RELATIONSHIP
The INT, FRAC, and MOD values, in conjunction with the
R counter, make it possible to generate output frequencies that
are spaced by fractions of the phase frequency detector (PFD).
See the RF Synthesizer: A Worked Example section for more
information. The RF VCO frequency (RF
where RF
controlled oscillator (VCO).
where:
REF
D is the REF
R is the preset divide ratio of binary 4-bit programmable
reference counter (1 to 15).
INT is the preset divide ratio of binary 9-bit counter (31 to 511).
MOD is the preset fractional modulus (2 to 4095).
FRAC is the numerator of the fractional division (0 to MOD − 1).
RF R COUNTER
The 4-bit RF R counter allows the input reference frequency
(REF
the PFD. Division ratios from 1 to 15 are allowed.
INPUT STAGE
IN
RF
F
IN
FROM RF
PFD
is the reference input frequency.
) to be divided down to produce the reference clock to
OUT
= RF
OUT
= F
IN
is the output frequency of external voltage
IN
PFD
doubler bit.
RF N DIVIDER
× (1 + D)/R
× (INT + (FRAC/MOD))
N-COUNTER
REG
INT
Figure 13. RF N Divider
MOD
REG
N = INT + FRAC/MOD
INTERPOLATOR
THIRD ORDER
FRACTIONAL
OUT
) equation is
VALUE
FRAC
TO PFD
(1)
(2)