ADF4150HVBCPZ AD [Analog Devices], ADF4150HVBCPZ Datasheet
ADF4150HVBCPZ
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ADF4150HVBCPZ Summary of contents
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FEATURES Fractional-N synthesizer and integer-N synthesizer High voltage charge pump Tuning range: 1 (or ±1 V from V RF bandwidth to 3.0 GHz Programmable divide-by-1/-2/-4/-8/-16 outputs Synthesizer power ...
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ADF4150HV TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Timing Characteristics ................................................................ 5 Absolute Maximum Ratings ............................................................ 6 Transistor Count ........................................................................... 6 Thermal ...
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SPECIFICATIONS SDV = 3.3 V ± 10 range is −40°C to +85°C. Table 1. Parameter REF CHARACTERISTICS IN Input Frequency Input Sensitivity Input Capacitance Input Current RF INPUT CHARACTERISTICS RF Input Frequency ...
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ADF4150HV Parameter RF OUTPUT CHARACTERISTICS Output Frequency Using RF Output Dividers Harmonic Content (Second) Harmonic Content (Third) 2 Minimum RF Output Power 2 Maximum RF Output Power Output Power Variation vs. Supply Output Power Variation vs. Temperature Level of Signal ...
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TIMING CHARACTERISTICS SDV = 3.3 V ± 10 range is −40°C to +85°C. Table 2. Parameter Limit ...
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ADF4150HV ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 3. Parameter Rating GND −0 +3 −0 +0 GND −0.3 ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 5. Pin Function Descriptions Pin No. Mnemonic Description 12, 16, 17, GND Ground. All ground pins should be tied together. 23, 24, 30 CLK Serial Clock Input. Data is ...
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ADF4150HV Pin No. Mnemonic Description 27 MUXOUT Multiplexer Output. The multiplexer output allows the lock detect, the N divider value, or the R counter value to be accessed externally. 28 SDV Digital Σ-Δ Modulator Power Supply. Place decoupling capacitors to ...
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TYPICAL PERFORMANCE CHARACTERISTICS 600 550 500 450 400 400µA SOURCE 350 350µA SOURCE 300 300µA SOURCE 250µA SOURCE 250 200 200µA SOURCE 150 I CP ...
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ADF4150HV –40 25MHz 75MHz 50MHz 100MHz –50 –60 –70 –80 –90 –100 –110 –120 1000 1200 1400 1600 FREQUENCY (MHz) Figure 10. PFD and Reference Spur Levels vs. Frequency at VCO Output, REF = 100 MHz, PFD = 25 MHz ...
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CIRCUIT DESCRIPTION REFERENCE INPUT SECTION The reference input stage is shown in Figure 14. The SW1 and SW2 switches are normally closed. The SW3 switch is normally open. When power-down is initiated, SW3 is closed, and SW1 and SW2 are ...
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ADF4150HV MUXOUT AND LOCK DETECT The multiplexer output on the ADF4150HV access various internal points on the chip. The state of MUXOUT is controlled by the M3, M2, and M1 bits in Register 2 (see Figure 22). Figure 17 shows ...
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REGISTER MAPS 16-BIT INTEGER VALUE (INT) DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 0 N16 N15 N14 N13 ...
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ADF4150HV 16-BIT INTEGER VALUE (INT) DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 0 N16 N15 N14 N13 N12 N11 ...
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LOW NOISE AND LOW SPUR MUXOUT MODES DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 ...
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ADF4150HV RESERVED DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 D13 ...
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REGISTER 0 Control Bits When Bits[C3:C1] are set to 000, Register 0 is programmed. Figure 20 shows the input data format for programming this register. 16-Bit Integer Value (INT) The 16 INT bits (Bits[DB30:DB15]) set the INT value, which determines ...
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ADF4150HV Reference Doubler Setting the DB25 bit to 0 disables the doubler and feeds the REF signal directly into the 10-bit R counter. Setting this bit multiplies the REF frequency by a factor of 2 before feeding ...
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REGISTER 3 Control Bits When Bits[C3:C1] are set to 011, Register 3 is programmed. Figure 23 shows the input data format for programming this register. Boost Enable Setting the DB18 bit to 1 enables the charge pump boost mode. If ...
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ADF4150HV RF SYNTHESIZER—A WORKED EXAMPLE The following equations are used to program the synthesizer [INT + (FRAC/MOD)] × (f OUT where the RF frequency output. OUT INT is the integer division factor. FRAC is the fractionality. ...
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SPURIOUS OPTIMIZATION AND BOOST MODE Narrow loop bandwidths can filter unwanted spurious signals, but these bandwidths usually have a long lock time. A wider loop bandwidth achieves faster lock times, but may lead to increased spurious signals inside the loop ...
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ADF4150HV PHASE RESYNC The output of a fractional-N PLL can settle to any one of the MOD phase offsets with respect to the input reference, where MOD is the fractional modulus. The phase resync feature of the ADF4150HV produces a ...
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APPLICATIONS INFORMATION ULTRAWIDEBAND PLL When paired with an octave tuning range VCO, the provides an ultrawideband PLL function using the on-board RF dividers. With an octave tuning range at the fundamental frequency, the RF dividers provide full frequency coverage with ...
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ADF4150HV 10pF VDD1 VDD2 RFOUT ADF5001 PRESCALER RFIN RFOUT GND 150Ω GENERATING THE HIGH VOLTAGE SUPPLY It is possible to use a boost converter such as the Analog Devices ADP1613 to generate the high voltage charge pump supply from a ...
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INTERFACING TO THE ADuC702x AND THE ADSP-BF527 The ADF4150HV has a simple SPI-compatible serial interface for writing to the device. The CLK, DATA, and LE pins control the data transfer. When LE goes high, the 32 bits that were clocked ...
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ADF4150HV OUTPUT MATCHING The output of the ADF4150HV can be matched in a number of ways for optimum operation; the most basic is to connect a 50 Ω resistor bypass capacitor of 100 pF is ...
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... OUTLINE DIMENSIONS PIN 1 INDICATOR 0.80 0.75 0.70 SEATING PLANE ORDERING GUIDE Model 1 Temperature Range ADF4150HVBCPZ −40°C to +85°C ADF4150HVBCPZ-RL7 −40°C to +85°C EVAL-ADF4150HVEB1Z RoHS Compliant Part. 5.10 0.30 5.00 SQ 0.25 4.90 0. 0.50 BSC 17 16 0.50 TOP VIEW BOTTOM VIEW 0.40 0.30 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF COMPLIANT TO JEDEC STANDARDS MO-220-WHHD. ...
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ADF4150HV NOTES ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09058-0-8/11(0) Rev Page ...