ADF4150HVBCPZ AD [Analog Devices], ADF4150HVBCPZ Datasheet - Page 17

• Manufacturer Part Number: ADF4150HVBCPZ
• Description: High Voltage, Fractional-N
• Manufacturer: AD [Analog Devices]

REGISTER 0
Control Bits
When Bits[C3:C1] are set to 000, Register 0 is programmed.
Figure 20 shows the input data format for programming this
register.
16-Bit Integer Value (INT)
The 16 INT bits (Bits[DB30:DB15]) set the INT value, which
determines the integer part of the feedback division factor. The
INT value is used in Equation 1 (see the INT, FRAC, MOD, and
R Counter Relationship section). Integer values from 23 to
32,767 are allowed for the 4/5 prescaler; for the 8/9 prescaler,
the minimum integer value is 75 and the maximum value is
65,535.
12-Bit Fractional Value (FRAC)
The 12 FRAC bits (Bits[DB14:DB3]) set the numerator of the
fraction that is input to the Σ-Δ modulator. This fraction, along
with the INT value, specifies the new frequency channel that
the synthesizer locks to, as shown in the RF Synthesizer—A
Worked Example section. FRAC values from 0 to (MOD − 1)
cover channels over a frequency range equal to the PFD refer-
ence frequency.
REGISTER 1
Control Bits
When Bits[C3:C1] are set to 001, Register 1 is programmed.
Figure 21 shows the input data format for programming this
register.
Prescaler Value
The dual-modulus prescaler, along with the INT, FRAC, and
MOD values, determines the overall division ratio from the VCO
output to the PFD input. The PR1 bit (DB27) in Register 1 sets
the prescaler value.
Operating at CML levels, the prescaler takes the clock from the
VCO output and divides it down for the counters. The prescaler
is based on a synchronous 4/5 core. When the prescaler is set to
4/5, the maximum RF frequency allowed is 3 GHz. Therefore,
when operating the
must be set to 8/9. The prescaler limits the INT value as follows:
•
•
12-Bit Phase Value
Bits[DB26:DB15] control the phase word. The word must be
less than the MOD value programmed in Register 1. The phase
word is used to program the RF output phase from 0° to 360°
with a resolution of 360°/MOD. For more information, see the
Phase Resync section.
Prescaler = 4/5: N
Prescaler = 8/9: N
ADF4150HV
MIN
MIN
= 23
= 75
above 3 GHz, the prescaler
Rev. 0 | Page 17 of 28
In most applications, the phase relationship between the RF
signal and the reference is not important. In such applications,
the phase value can be used to optimize the fractional and
subfractional spur levels. For more information, see the Spur
Consistency and Fractional Spur Optimization section.
If neither the phase resync nor the spurious optimization function
is used, it is recommended that the phase word be set to 1.
12-Bit Modulus Value (MOD)
The 12 MOD bits (Bits[DB14:DB3]) set the fractional modulus.
The fractional modulus is the ratio of the PFD frequency to the
channel step resolution on the RF output. For more information,
see the 12-Bit Programmable Modulus section.
REGISTER 2
Control Bits
When Bits[C3:C1] are set to 010, Register 2 is programmed.
Figure 22 shows the input data format for programming this
register.
Low Noise and Low Spur Modes
The noise modes on the
Bits[DB30:DB29] in Register 2 (see Figure 22). The noise modes
allow the user to optimize a design either for improved spurious
performance or for improved phase noise performance.
When the low spur mode is chosen, dither is enabled. Dither
randomizes the fractional quantization noise so that it resembles
white noise rather than spurious noise. As a result, the part is
optimized for improved spurious performance. Low spur mode
is normally used for fast-locking applications when the PLL
closed-loop bandwidth is wide. Wide loop bandwidth is a loop
bandwidth greater than 1/10 of the RF
tion (f
same level as a narrow loop bandwidth.
For best noise performance, use the low noise mode option.
When the low noise mode is chosen, dither is disabled. This
mode ensures that the charge pump operates in an optimum
region for noise performance. Low noise mode is extremely
useful when a narrow loop filter bandwidth is available. The
synthesizer ensures extremely low noise, and the filter attenu-
ates the spurs.
Figure 8 and Figure 9 show fractional spur levels when using
low spur mode and low noise mode. Figure 12 shows the in-band
phase noise when using low spur mode and low noise mode.
MUXOUT
The on-chip multiplexer is controlled by Bits[DB28:DB26] (see
Figure 22).
RES
). A wide loop filter does not attenuate the spurs to the
ADF4150HV
OUT
are controlled by setting
channel step resolu-
ADF4150HV