ADF4150HVBCPZ AD [Analog Devices], ADF4150HVBCPZ Datasheet - Page 25

• Manufacturer Part Number: ADF4150HVBCPZ
• Description: High Voltage, Fractional-N
• Manufacturer: AD [Analog Devices]

INTERFACING TO THE ADuC702x AND
THE ADSP-BF527
The
writing to the device. The CLK, DATA, and LE pins control the
data transfer. When LE goes high, the 32 bits that were clocked
into the appropriate register on each rising edge of CLK are
transferred to the appropriate latch. See Figure 2 for the timing
diagram and Table 6 for the register address table.
ADuC702x Interface
Figure 31 shows the interface between the
ADuC702x
family is based on an ARM7 core, but the same interface can be
used with any 8051-based microcontroller.
The microcontroller is set up for SPI master mode with CPHA =
0. To initiate the operation, the I/O port driving LE is brought
low. Each latch of the
is accomplished by writing four 8-bit bytes from the micro-
controller to the device. After the fourth byte is written, the
LE input should be brought high to complete the transfer.
I/O port lines on the
power-down input (CE) and the lock detect (MUXOUT con-
figured for lock detect and polled by the port input). When
operating in the mode described, the maximum SPI transfer
rate of the
mum rate at which the output frequency can be changed is
833 kHz. If using a faster SPI clock, make sure that the SPI
timing requirements listed in Table 2 are adhered to.
ADF4150HV
ADuC702x
I/O PORTS
ADuC7023
family of analog microcontrollers. The
SCLOCK
Figure 31.
MOSI
has a simple SPI-compatible serial interface for
ADuC702x
ADuC702x
ADF4150HV
is 20 Mbps. This means that the maxi-
to
ADF4150HV
are also used to control the
needs a 32-bit word, which
CLK
DATA
LE
CE
MUXOUT
(LOCK DETECT)
ADF4150HV
ADF4150HV
Interface
ADuC702x
and the
Rev. 0 | Page 25 of 28
Blackfin ADSP-BF527 Interface
Figure 32 shows the interface between the
the Blackfin®
ADF4150HV
The easiest way to accomplish this using the Blackfin family
is to use the autobuffered transmit mode of operation with
alternate framing. This mode provides a means for transmitting
an entire block of serial data before an interrupt is generated.
Set up the word length for eight bits and use four memory loca-
tions for each 32-bit word. To program each 32-bit latch, store
the 8-bit bytes, enable the autobuffered mode, and write to the
transmit register of the DSP. This last operation initiates the
autobuffer transfer. If using a faster SPI clock, make sure that
the SPI timing requirements listed in Table 2 are adhered to.
PCB DESIGN GUIDELINES FOR A CHIP SCALE
PACKAGE
The lands on the chip scale package (CP-32-11) are rectangular.
The PCB pad for these lands must be 0.1 mm longer than the
package land length and 0.05 mm wider than the package land
width. Each land must be centered on the pad to ensure that the
solder joint size is maximized.
The bottom of the chip scale package has a central exposed
thermal pad. The thermal pad on the PCB must be at least as
large as the exposed pad. On the PCB, there must be a minimum
clearance of 0.25 mm between the thermal pad and the inner
edges of the pad pattern to ensure that shorting is avoided.
Thermal vias can be used on the PCB thermal pad to improve
the thermal performance of the package. If vias are used, they
must be incorporated into the thermal pad at 1.2 mm pitch grid.
The via diameter must be between 0.3 mm and 0.33 mm, and
the via barrel must be plated with 1 oz. of copper to plug the via.
ADSP-BF527
I/O PORTS
Figure 32.
ADSP-BF527
needs a 32-bit serial word for each latch write.
MOSI
GPIO
SCK
ADSP-BF527
digital signal processor (DSP). The
to
ADF4150HV
CLK
DATA
LE
CE
MUXOUT
(LOCK DETECT)
ADF4150HV
ADF4150HV
Interface
ADF4150HV
and