ADF4150HVBCPZ AD [Analog Devices], ADF4150HVBCPZ Datasheet - Page 4

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ADF4150HVBCPZ

Manufacturer Part Number
ADF4150HVBCPZ
Description
High Voltage, Fractional-N
Manufacturer
AD [Analog Devices]
Datasheet
ADF4150HV
Parameter
RF OUTPUT CHARACTERISTICS
NOISE CHARACTERISTICS
1
2
3
4
T
Using 50 Ω resistors to AV
This figure can be used to calculate phase noise for any application. To calculate in-band phase noise performance as seen at the VCO output, use the following formula:
PN
The PLL phase noise is composed of flicker (1/f) noise plus the normalized PLL noise floor. The flicker noise is specified at a 10 kHz offset and normalized to 1 GHz. The
formula for calculating the 1/f noise contribution at an RF frequency (f
the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.
A
Output Frequency Using RF Output
Harmonic Content (Second)
Harmonic Content (Third)
Minimum RF Output Power
Maximum RF Output Power
Output Power Variation vs. Supply
Output Power Variation vs. Temperature
Level of Signal with RF Mute Enabled
Normalized In-Band Phase Noise
Normalized 1/f Noise (PN
RF Output Divider Noise Floor
Spurious Signals Due to PFD Frequency
= 25°C; AV
SYNTH
Dividers
Floor (PN
= PN
TOT
DD
− 10 log(f
= DV
SYNTH
DD
)
3
= 3.3 V; prescaler = 8/9; f
PFD
DD
) − 20 log N.
, into a 50 Ω load.
1_f
)
2
2
4
REFIN
Min
31.25
= 100 MHz; f
PFD
Typ
−19
−20
−13
−10
−4
5
±1
±1
−37
−213
−203
−113
−108
−155
−70
−85
= 25 MHz; f
RF
) and at a frequency offset (f) is given by PN = PN
Rev. 0 | Page 4 of 28
RF
= 1.75 GHz.
Max
Unit
MHz
dBc
dBc
dBc
dBc
dBm
dBm
dB
dB
dBm
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc
dBc
Test Conditions/Comments
500 MHz VCO input and divide-by-16 selected
Fundamental VCO output
Divided VCO output
Fundamental VCO output
Divided VCO output
Programmable in 3 dB steps
Programmable in 3 dB steps
Pull-up supply on Pin 18 and Pin 19 varied
from 3.0 V to 3.6 V
From −40°C to +85°C
Low noise mode
Low spur mode
Low noise mode
Low spur mode
Measured at 10 MHz offset
At RF
At VCO output
PDB
RF
OUT
pin brought low; RF = 2 GHz
+/RF
1_f
+ 10 log(10 kHz/f) + 20 log(f
OUT
− pins
RF
/1 GHz). Both

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