ADF4150HVBCPZ AD [Analog Devices], ADF4150HVBCPZ Datasheet - Page 7

• Manufacturer Part Number: ADF4150HVBCPZ
• Description: High Voltage, Fractional-N
• Manufacturer: AD [Analog Devices]

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 5. Pin Function Descriptions
Pin No.
1, 7, 8, 12, 16, 17,
23, 24, 30, 32
2
3
4
5
6
9
10
11, 13, 20
14
15
18
19
21
22
25
26
Mnemonic
GND
CLK
DATA
LE
CE
V
CP
CP
AV
RF
RF
RF
RF
PDB
DV
REF
LD
P
IN
IN
OUT
OUT
OUT
GND
DD
DD
+
−
IN
RF
−
+
Description
Ground. All ground pins should be tied together.
Serial Clock Input. Data is clocked into the 32-bit shift register on the CLK rising edge. This input is a high
impedance CMOS input.
Serial Data Input. The serial data is loaded MSB first with the three LSBs as the control bits. This input is a
high impedance CMOS input.
Load Enable. When LE goes high, the data stored in the 32-bit shift register is loaded into the register
that is selected by the three control bits. This input is a high impedance CMOS input.
Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state
mode. A logic high on this pin powers up the device.
High Voltage Charge Pump Power Supply. Place decoupling capacitors to the ground plane as close to
this pin as possible. The decoupling capacitors should have the appropriate voltage rating (a value of
10 μF is recommended). Care should be taken to ensure that V
ratings on power-up (see Table 3). A 10 Ω series resistor can help to significantly reduce voltage overshoot
with minimal IR drop.
High Voltage Charge Pump Output. When enabled, this output provides ±I
filter. The output of the loop filter is connected to the voltage tuning port of the external VCO.
High Voltage Charge Pump Ground. All ground pins should be tied together.
Analog Power Supply. This pin ranges from 3.0 V to 3.6 V. Place decoupling capacitors to the ground
plane as close to this pin as possible. AV
Positive RF Input. The output of the VCO or external prescaler should be ac-coupled to this pin.
Complementary RF Input. If a single-ended input is required, this pin can be tied to ground via a 100 pF
capacitor.
Divided-Down Output of RF
required.
Divided-Down Output of RF
required.
RF Power-Down. A logic low on this pin mutes the RF outputs. This function is also software controllable.
Digital Power Supply. Place decoupling capacitors to the ground plane as close to this pin as possible.
DV
Reference Input. This CMOS input has a nominal threshold of AV
of 100 kΩ. This input can be driven from a crystal oscillator, TCXO, or other reference.
Lock Detect Output. A logic high output on this pin indicates PLL lock. A logic low output indicates loss
of PLL lock.
DD
must have the same value as AV
DATA
NOTES
1. THE LFCSP HAS AN EXPOSED PAD
GND
GND
GND
CLK
THAT MUST BE CONNECTED TO GND.
CE
LE
V
P
1
2
3
4
5
6
7
8
Figure 3. Pin Configuration
Rev. 0 | Page 7 of 28
ADF4150HV
(Not to Scale)
IN
IN
TOP VIEW
−. This pin can be left unconnected if the divider functionality is not
+. This pin can be left unconnected if the divider functionality is not
DD
.
DD
must have the same value as DV
24 GND
23 GND
22 DV
21 PDB
20 AV
19 RF
18 RF
17 GND
OUT
OUT
DD
DD
RF
+
–
P
DD
does not exceed the absolute maximum
/2 and a dc equivalent input resistance
CP
DD
.
to the external passive loop
ADF4150HV