ADF4111 AD [Analog Devices], ADF4111 Datasheet
ADF4111
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ADF4111 Summary of contents
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... FEATURES ADF4110: 550 MHz ADF4111: 1.2 GHz ADF4112: 3.0 GHz ADF4113: 4.0 GHz 2 5.5 V Power Supply Separate Charge Pump Supply (V Tuning Voltage Systems Programmable Dual Modulus Prescaler 8/9, 16/17, 32/33, 64/65 Programmable Charge Pump Currents Programmable Antibacklash Pulsewidth 3-Wire Serial Interface Analog and Digital Lock Detect Hardware and Software Power-Down Mode ...
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... Output Low Voltage OL POWER SUPPLIES ( ADF4110 ADF4111 ADF4112 ADF4113 I P Low Power Sleep Mode ≤ V ≤ 6.0 V; AGND = DGND = CPGND = Version B Chips Unit 45/550 45/550 MHz min/max 25/550 25/550 MHz min/max 0.045/1.2 ...
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... ADF4110 = 540 MHz; RF for ADF4111, ADF4112, ADF4113 = 900 MHz 540 MHz 2700; Loop B kHz 900 MHz 4500; Loop B kHz 836 MHz 27867; Loop B kHz 1750 MHz ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumu- late on the human body and test equipment and can discharge without detection. Although the ADF4110/ADF4111/ADF4112/ADF4113 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... and an equivalent input resis- DD must be the same value systems where V DD CHIP SCALE PACKAGE 1 15 CPGND MUXOUT ADF4110 ADF4111 14 AGND 2 LE ADF4112 AGND 3 13 DATA ADF4113 TOP VIEW CLK IN (Not to Scale) ...
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... ADF4110/ADF4111/ADF4112/ADF4113 FREQ-UNIT PARAM-TYPE DATA-FORMAT KEYWORD GHz FREQ MAGS11 ANGS11 FREQ MAGS11 0.05 0.89207 –2.0571 1.05 0.9512 0.10 0.8886 –4.4427 1.10 0.93458 0.15 0.89022 –6.3212 1.15 0.94782 0.20 0.96323 –2.1393 1.20 0.96875 0.25 0.90566 –12.13 1.25 0.92216 0.30 0.90307 –13.52 1.30 0.93755 0.35 0.89318 –15.746 1.35 0.96178 0.40 0.89806 –18.056 1 ...
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... SWEEP = 477ms –50 AVERAGES = 10 –60 –70 –80 –75.2dBc/Hz –90 –100 –400Hz –200Hz 1750MHz Figure 10. ADF4113 Phase Noise (1750 MHz, 30 kHz, 3 kHz) REV. 0 ADF4110/ADF4111/ADF4112/ADF4113 10dB/DIVISION – –50 –60 –70 –80 –90 –100 –110 –90.2dBc –120 –130 –140 +200kHz ...
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... ADF4110/ADF4111/ADF4112/ADF4113 10dB/DIVISION –40dBc/Hz –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 100Hz FREQUENCY OFFSET FROM 3100MHz CARRIER Figure 14. ADF4113 Integrated Phase Noise (3100 MHz, 1 MHz, 100 kHz 3V REFERENCE – 5mA LEVEL = –17.2dBm CP PFD FREQUENCY = 1MHz – ...
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... ADF4110 ADF4111 100 Figure 22 2.0 1.5 1.0 0 100 0 Figure 23. DI (ADF4110, ADF4111, ADF4112, ADF4113) –9– ADF4113 ADF4112 8/9 16/17 32/33 PRESCALER VALUE vs. Prescaler Value 100 150 PRESCALER OUTPUT FREQUENCY – MHz vs. Prescaler Output Frequency DD 64/65 200 ...
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... ADF4110/ADF4111/ADF4112/ADF4113 CIRCUIT DESCRIPTION REFERENCE INPUT SECTION The reference input stage is shown in Figure 24. SW1 and SW2 are normally-closed switches. SW3 is normally-open. When power-down is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures that there is no loading of the REF on power-down. POWER-DOWN ...
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... With LDP set to 1, five consecutive cycles of less than 15 ns are required to set the lock detect. It will stay set high until a phase error of greater than detected on any subsequent PD cycle. REV. 0 ADF4110/ADF4111/ADF4112/ADF4113 The N-channel open-drain analog lock detect should be oper CHARGE ated with an external pull-up resistor of 10 kΩ ...
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... ADF4110/ADF4111/ADF4112/ADF4113 ANTI- TEST BACKLASH DLY SYNC MODE BITS WIDTH DB18 DB17 DB23 DB22 DB21 DB20 DB19 X DLY SYNC LDP T2 T1 ABP2 ABP1 X = DON'T CARE RESERVED DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 B13 B12 B11 B10 X = DON'T CARE ...
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... OUTPUT OF PRESCALER IS RESYNCHRONIZED WITH NONDELAYED VERSION OF RF INPUT 1 0 NORMAL OPERATION 1 1 OUTPUT OF PRESCALER IS RESYNCHRONIZED WITH DELAYED VERSION OF RF INPUT REV. 0 ADF4110/ADF4111/ADF4112/ADF4113 Table III. Reference Counter Latch Map 14-BIT REFERENCE COUNTER DB15 DB14 DB13 DB12 DB11 DB10 DB9 R14 R13 R12 ...
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... ADF4110/ADF4111/ADF4112/ADF4113 RESERVED DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 B13 B12 B11 B10 X = DON'T CARE B13 B12 • • • • • • (FUNCTION LATCH) CP GAIN FASTLOCK ENABLE* ...
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... ASYNCHRONOUS POWER-DOWN SYNCHRONOUS POWER-DOWN P2 P1 PRESCALER VALUE 8 16/17 32/ 64/65 REV. 0 ADF4110/ADF4111/ADF4112/ADF4113 Table V. Function Latch Map CURRENT SETTTING TIMER COUNTER 1 CONTROL DB13 DB12 DB11 DB10 DB9 CPI2 CPI1 TC4 TC3 TC2 TC1 FASTLOCK MODE FASTLOCK DISABLED ...
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... ADF4110/ADF4111/ADF4112/ADF4113 CURRENT CURRENT PRESCALER SETTTING SETTTING VALUE 2 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 P2 P1 PD2 CPI6 CPI5 CPI4 CPI3 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 PIN PD2 PD1 MODE ASYNCHRONOUS POWER- ...
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... The device enters Fastlock by having a “1” written to the CP Gain bit in the AB counter latch. The device exits Fastlock by having a “0” written to the CP Gain bit in the AB counter latch. REV. 0 ADF4110/ADF4111/ADF4112/ADF4113 Fastlock Mode 2 The charge pump current is switched to the contents of Current Setting 2. ...
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... ADF4110/ADF4111/ADF4112/ADF4113 THE INITIALIZATION LATCH When C2 the Initialization Latch is programmed. This is essentially the same as the Function Latch (programmed when C2 0). However, when the Initialization Latch is programmed an addi- tional internal reset pulse is applied to the R and AB counters. This pulse ensures that the AB counter is at load point when the AB counter data is latched and the device will begin counting in close phase alignment ...
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... GSM standard), the reference input must be divided by 65, using the on-chip reference divider of the ADF4111/ADF4112/ADF4113. The charge pump output of the ADF4111/ADF4112/ADF4113 (Pin 2) drives the loop filter. In calculating the loop filter com- ponent values, a number of items need to be considered. In this example, the loop filter was designed so that the overall phase margin for the system would be 45 degrees ...
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... ADF4110/ADF4111/ADF4112/ADF4113 8 FREF REF IN IN ADF4111 ADF4112 ADF4113 CE CLK DATA SET 2.7k AD5320 12-BIT V-OUT DAC SPI COMPATIBLE SERIAL BUS Figure 30. Driving the R USING A D/A CONVERTER TO DRIVE R You can use a D/A converter to drive the R ADF4110 family and thus increase the level of control over the charge pump current I ...
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... REF IN IN ADF4110 ADF4111 ADF4112 ADF4113 1000pF 1000pF FREF REF ADF4113 CE CLK MUXOUT DATA REV. 0 ADF4110/ADF4111/ADF4112/ADF4113 V P POWER-DOWN CONTROL LOOP CP FILTER 1 R SET 4.7k 100pF 100pF DECOUPLING CAPACITORS AND INTERFACE SIGNALS HAVE BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY ...
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... ADF4110/ADF4111/ADF4112/ADF4113 DIRECT CONVERSION MODULATOR In some applications a direct conversion architecture can be used in base station transmitters. Figure 33 shows the combination available from ADI to implement this solution. The circuit diagram shows the AD9761 being used with the AD8346. The use of dual integrated DACs such as the AD9761 with specified ± ...
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... To program each 24-bit latch, store the three 8-bit bytes, enable the Autobuffered mode and then write to the transmit register of the DSP. This last operation initiates the autobuffer transfer. ADF4110 ADF4111 ADF4112 ADF4113 –23– SCLK SCLK SDATA DT ADF4110 ADF4111 TFS LE ADF4112 ADF4113 CE MUXOUT (LOCK DETECT) ...
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... ADF4110/ADF4111/ADF4112/ADF4113 0.159 (4.05) 0.157 (4.00) 0.156 (3.95) 0.039 (1.00) 0.035 (0.90) 0.031 (0.80) SEATING OUTLINE DIMENSIONS Dimensions shown in inches and (mm). Chip Scale (CP-20) 0.159 (4.05) 0.079 (2.0) REF 0.157 (4.00) 0.156 (3.95) 0.018 (0.45) 0.016 (0.40 0.014 (0.35) DETAIL E TOP VIEW 0.020 (0.5) REF LEAD PITCH 11 10 BOTTOM VIEW 0.0083 (0.211) (ROTATED 180 ) 0.0079 (0.200) ...