ADF4111 AD [Analog Devices], ADF4111 Datasheet - Page 18

• Manufacturer Part Number: ADF4111
• Description: RF PLL Frequency Synthesizers
• Manufacturer: AD [Analog Devices]

ADF4110/ADF4111/ADF4112/ADF4113
THE INITIALIZATION LATCH
When C2, C1 = 1, 1, the Initialization Latch is programmed.
This is essentially the same as the Function Latch (programmed
when C2, C1 = 1, 0).
However, when the Initialization Latch is programmed an addi-
tional internal reset pulse is applied to the R and AB counters.
This pulse ensures that the AB counter is at load point when the
AB counter data is latched and the device will begin counting in
close phase alignment.
If the Latch is programmed for synchronous power-down (CE
pin is High; PD1 bit is High; PD2 bit is Low), the internal pulse
also triggers this power-down. The prescaler reference and the
oscillator input buffer are unaffected by the internal reset pulse and
so close phase alignment is maintained when counting resumes.
When the first AB counter data is latched after initialization, the
internal reset pulse is again activated. However, successive AB
counter loads after this will not trigger the internal reset pulse.
DEVICE PROGRAMMING AFTER INITIAL POWER-UP
After initially powering up the device, there are three ways to
program the device.
Initialization Latch Method
Apply V
of input word). Make sure that F1 bit is programmed to “0.”
Then do an R load (“00” in 2 LSBs). Then do an AB load (“01”
in 2 LSBs).
When the Initialization Latch is loaded, the following occurs:
1. The function latch contents are loaded.
2. An internal pulse resets the R, A, B, and timeout counters
3. Latching the first AB counter data after the initialization word
The CE Pin Method
Apply V
Bring CE low to put the device into power-down. This is an
asynchronous power-down in that it happens immediately.
Program the Function Latch (10). Program the R Counter Latch
(00). Program the AB Counter Latch (01).
Bring CE high to take the device out of power-down. The R
and AB counters will now resume counting in close alignment.
Note that after CE goes high, a duration of 1 µs may be required
for the prescaler bandgap voltage and oscillator input buffer bias
to reach steady state.
to load state conditions and also three-states the charge pump.
Note that the prescaler bandgap reference and the oscillator
input buffer are unaffected by the internal reset pulse, allow-
ing close phase alignment when counting resumes.
will activate the same internal reset pulse. Successive AB loads
will not trigger the internal reset pulse unless there is another
initialization.
DD
DD
.
. Program the Initialization Latch (“11” in 2 LSBs
–18–
CE can be used to power the device up and down in order to
check for channel activity. The input register does not need to
be reprogrammed each time the device is disabled and enabled
as long as it has been programmed at least once after V
initially applied.
The Counter Reset Method
Apply V
Do a Function Latch Load (“10” in 2 LSBs). As part of this, load
“1” to the F1 bit. This enables the counter reset.
Do an R Counter Load (“00” in 2 LSBs) Do an AB Counter Load
(“01” in 2 LSBs). Do a Function Latch Load (“10” in 2 LSBs).
As part of this, load “0” to the F1 bit. This disables the counter
reset.
This sequence provides the same close alignment as the initial-
ization method. It offers direct control over the internal reset.
Note that counter reset holds the counters at load point and three-
states the charge pump, but does not trigger synchronous power-
down. The counter reset method requires an extra function latch
load compared to the initialization latch method.
RESYNCHRONIZING THE PRESCALER OUTPUT
Table III (the Reference Counter Latch Map) shows two bits,
DB22 and DB21 that are labelled DLY and SYNC respectively.
These bits affect the operation of the prescaler.
With SYNC = “1,” the prescaler output is resynchronized with
the RF input. This has the effect of reducing jitter due to the
prescaler and can lead to an overall improvement in synthesizer
phase noise performance. Typically, a 1 dB to 2 dB improve-
ment is seen in the ADF4113. The lower bandwidth devices can
show an even greater improvement. For example, the ADF4110
phase noise is typically improved by 3 dB when SYNC is enabled.
With DLY = “1,” the prescaler output is resynchronized with a
delayed version of the RF input.
If the SYNC feature is used on the synthesizer, some care must
be taken. At some point, (at certain temperatures and output
frequencies), the delay through the prescaler will coincide with
the active edge on RF input and this will cause the SYNC fea-
ture to break down. So, it is important when using the SYNC
feature to be aware of this. Adding a delay to the RF signal, by
programming DLY = “1,” will extend the operating frequency
and temperature somewhat. Using the SYNC feature will also
increase the value of the AI
output, the ADF4113 AI
SYNC is enabled and a further 0.3 mA if DLY is enabled.
All the typical performance plots on the data sheet except for
Figure 5 apply for DLY and SYNC = “0,” i.e., no resynchroniza-
tion or delay enabled.
DD
.
DD
DD
increases by about 1.3 mA when
for the device. With a 900 MHz
DD
REV. 0
was