ADF4111 AD [Analog Devices], ADF4111 Datasheet - Page 13

• Manufacturer Part Number: ADF4111
• Description: RF PLL Frequency Synthesizers
• Manufacturer: AD [Analog Devices]

REV. 0
DB23 DB22
X
X = DON'T
DLY
CARE
0
0
1
1
DLY
DLY
SYNC
0
1
0
1
SYNC
SYNC
DB21 DB20
LDP
0
1
NORMAL OPERATION
OUTPUT OF PRESCALER IS RESYNCHRONIZED
WITH NONDELAYED VERSION OF RF INPUT
NORMAL OPERATION
OUTPUT OF PRESCALER IS RESYNCHRONIZED
WITH DELAYED VERSION OF RF INPUT
OPERATION
LDP
OPERATION
THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
DB19 DB18
MODE BITS
T2
TEST
TEST MODE BITS SHOULD
BE SET TO 00 FOR NORMAL
OPERATION
T1
ABP2
0
0
1
1
ABP2 ABP1
DB17 DB16
BACKLASH
WIDTH
ANTI-
ABP1
0
1
0
1
ANTIBACKLASH PULSEWIDTH
Table III. Reference Counter Latch Map
DB15 DB14
3.0ns
1.5ns
6.0ns
3.0ns
R14
R13
DB13
R12
DB12
R11
–13–
R14
0
0
0
0
1
1
1
1
•
•
•
DB11 DB10
R10
ADF4110/ADF4111/ADF4112/ADF4113
14-BIT REFERENCE COUNTER
R9
R13
0
0
0
0
1
1
1
1
•
•
•
DB9
R8
R12
0
0
0
0
1
1
1
1
•
•
•
DB8
R7
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
DB7
R6
DB6
R5
R3
0
0
0
1
1
1
1
1
•
•
•
DB5
R4
R2
0
1
1
0
0
0
1
1
•
•
•
DB4
R3
R1
DB3
1
0
1
0
0
1
0
1
R2
•
•
•
DB2
R1
DIVIDE RATIO
C2 (0) C1 (0)
DB1
16380
16381
16382
16383
CONTROL
1
2
3
4
•
•
•
BITS
DB0