ADF4157 AD [Analog Devices], ADF4157 Datasheet
ADF4157
Available stocks
Related parts for ADF4157
ADF4157 Summary of contents
Page 1
... Trademarks and registered trademarks are the property of their respective owners. High Resolution 6 GHz Fractional-N GENERAL DESCRIPTION The ADF4157 GHz fractional-N frequency synthesizer with a 25-bit fixed modulus, allowing subhertz frequency resolution at 6 GHz. It consists of a low noise digital phase frequency detector (PFD), a precision charge pump, and a programmable reference divider. There is a Σ ...
Page 2
... ADF4157 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Specifications .................................................................. 4 Absolute Maximum Ratings............................................................ 5 Thermal Resistance ...................................................................... 5 ESD Caution.................................................................................. 5 Pin Configurations and Function Descriptions ........................... 6 Typical Performance Characteristics ............................................. 7 Circuit Description........................................................................... 8 Reference Input Section............................................................... 8 RF Input Stage............................................................................... 8 RF INT Divider............................................................................. 8 25-Bit Fixed Modulus ...
Page 3
... VCO output. 5 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value). 6 The phase noise is measured with the EVAL-ADF4157EB1Z and the Agilent E5052A phase noise system 100 MHz MHz ...
Page 4
... ADF4157 TIMING SPECIFICATIONS 2 3 dBm referred to 50 Ω. Table 2. Parameter Limit MIN MAX CLK DATA DB23 (MSB 5.5 V; AGND = DGND = Version) ...
Page 5
... V to +5.8 V Package Type −0 0.3 V TSSOP DD −0 0.3 V LFCSP (Paddle Soldered) DD −0 0 ESD CAUTION −40°C to +85°C −65°C to +125°C 150°C 260°C 40 sec Rev Page ADF4157 θ Unit JA 112 °C/W 30.4 °C/W ...
Page 6
... CPMAX R SET has a value ± 10 has a value ± 10 Rev Page PIN 1 INDICATOR CPGND 1 15 MUXOUT 14 LE AGND 2 ADF4157 13 DATA AGND 3 TOP VIEW CLK IN (Not to Scale Figure 4. LFCSP Pin Configuration to the external loop filter which, in turn, drives ...
Page 7
... TIME (µs) with CSR On and Off CSR OFF CSR ON –100 0 100 200 300 400 500 600 TIME (µs) with CSR On and Off –2 –4 –6 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 V (V) CP ADF4157 700 800 900 700 800 900 4.0 4 ...
Page 8
... Figure 12. RF Input Stage RF INT DIVIDER The RF INT counter allows a division ratio in the PLL feedback counter. Division ratios from 23 to 4095 are allowed. 25-BIT FIXED MODULUS The ADF4157 has a 25-bit fixed modulus. This allows output frequencies to be spaced with a resolution ...
Page 9
... Q2 U2 –IN Figure 14. PFD Simplified Schematic MUXOUT AND LOCK DETECT The output multiplexer on the ADF4157 allows the user to access various internal points on the chip. The state of MUXOUT is controlled by M4, M3, M2, and M1 (see Figure 17). Figure 15 shows the MUXOUT section in block diagram form. ...
Page 10
... ADF4157 REGISTER MAPS MUXOUT 12-BIT INTEGER VALUE (INT) CONTROL DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 ...
Page 11
... Reserved Bit The reserved bit should be set to 0 for normal operation. MUXOUT The on-chip multiplexer is controlled by DB[30], DB[29], DB[28] and DB[27] on the ADF4157. See Figure 17 for the truth table. 12-Bit INT Value These twelve bits control what is loaded as the INT value. This is used to determine the overall feedback division factor ...
Page 12
... ADF4157 LSB FRAC REGISTER (R1) MAP With R1[ set to [0, 0, 1], the on-chip LSB FRAC register is programmed as shown in Figure 18. 13-Bit LSB FRAC Value These thirteen bits, along with Bits DB[14:3] in the INT/FRAC register (R0), control what is loaded as the FRAC value into the fractional interpolator. This is part of what determines the overall feedback division factor ...
Page 13
... Operating at CML levels, it takes the clock from the RF input stage and divides it down for the counters based on a synchronous 4/5 core. When set to 4/5, the maximum RF frequency allowed is 3 GHz. Therefore, when operating the ADF4157 above 3 GHz, the prescaler must be set to 8/9. The prescaler limits the INT value. With 23. ...
Page 14
... ADF4157 CURRENT SETTING DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 CPI4 CPI3 CPI2 CPI1 ...
Page 15
... DB[4] puts the charge pump into three-state mode when programmed should be set to 0 for normal operation. RF Counter Reset DB[3] is the RF counter reset bit for the ADF4157. When this is 1, the RF synthesizer counters are held in reset. For normal operation, this bit should be 0. ...
Page 16
... ADF4157 TEST REGISTER (R4) MAP With R3[ set to [1, 0, 0], the on-chip test register (R4) is programmed as shown in Figure 21. DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 ...
Page 17
... The ADF4157 contains a cycle slip reduction circuit to extend the linear range of the PFD, allowing faster lock times without loop filter changes. When the ADF4157 detects that a cycle slip is about to occur, it (4) turns on an extra charge pump current cell. This outputs a constant ...
Page 18
... PLL output the minimum slew rate specification of 400 V/μs is met. An appropriate LVDS driver can be used to square up the RF signal before it is fed back to the ADF4157 RF input. The FIN1001 from Fairchild Semiconductor is one such LVDS driver. FILTER DESIGN—ADIsimPLL A filter design and analysis program is available to help the user implement PLL design. Visit download of the ADIsimPLL™ ...
Page 19
... Thin Shrink Small Outline Package [TSSOP] ADF4157BRUZ-RL7 1 16-Lead Thin Shrink Small Outline Package [TSSOP] 1 ADF4157BCPZ 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 1 ADF4157BCPZ-RL 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 1 ADF4157BCPZ-RL7 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 1 EVAL-ADF4157EB1Z Evaluation Board RoHS Compliant Part. 5.10 5.00 4. ...
Page 20
... ADF4157 NOTES © 2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05874-0-7/07(0) Rev Page ...