ADF4157 AD [Analog Devices], ADF4157 Datasheet - Page 6

• Manufacturer Part Number: ADF4157
• Description: High Resolution 6 GHz Fractional-N Frequency Synthesizer
• Manufacturer: AD [Analog Devices]

ADF4157
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Table 5. Pin Function Descriptions
TSSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
LFCSP
19
20
1
2, 3
4
5
6, 7
8
9, 10
11
12
13
14
15
16, 17
18
CPGND
AGND
RF
RF
REF
AV
R
Figure 3. TSSOP Pin Configuration
SET
IN
IN
CP
DD
Mnemonic
R
CP
CPGND
AGND
RF
RF
AV
REF
DGND
CE
CLK
DATA
LE
MUXOUT
DV
V
IN
B
A
SET
P
IN
IN
DD
DD
1
2
3
4
5
6
7
8
IN
B
A
(Not to Scale)
ADF4157
TOP VIEW
Description
Connecting a resistor between this pin and ground sets the maximum charge pump output current.
The relationship between I
where:
R
I
Charge Pump Output. When enabled, this provides ±I
the external VCO.
Charge Pump Ground. This is the ground return path for the charge pump.
Analog Ground. This is the ground return path of the prescaler.
Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with
a small bypass capacitor, typically 100 pF.
Input to the RF Prescaler. This small-signal input is normally ac-coupled from the VCO.
Positive Power Supply for the RF Section. Decoupling capacitors to the digital ground plane should be
placed as close as possible to this pin. AV
DV
Reference Input. This is a CMOS input with a nominal threshold of V
resistance of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-
coupled.
Digital Ground.
Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-
state mode.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched
into the shift register on the CLK rising edge. This input is a high impedance CMOS input.
Serial Data Input. The serial data is loaded MSB first with the three LSBs being the control bits. This input is
a high impedance CMOS input.
Load Enable, CMOS Input. When LE is high, the data stored in the shift registers is loaded into one of
the five latches, the latch being selected using the control bits.
This multiplexer output allows the lock detect, the scaled RF, or the scaled reference frequency to be
accessed externally.
Positive Power Supply for the Digital Section. Decoupling capacitors to the digital ground plane should be
placed as close as possible to this pin. DV
AV
Charge Pump Power Supply. This should be greater than or equal to V
be set to 5.5 V and used to drive a VCO with a tuning range of up to 5.5 V.
CPMAX
SET
DD
DD
= 5.1 kΩ.
16
15
14
13
12
11
10
.
9
.
I
= 5 mA.
CPMAX
V
DV
MUXOUT
LE
DATA
CLK
CE
DGND
P
DD
=
25
R
SET
5 .
CP
Rev. 0 | Page 6 of 20
and R
SET
is
DD
DD
has a value of 3 V ± 10%. AV
has a value of 3 V ± 10%. DV
CP
CPGND
to the external loop filter which, in turn, drives
AGND
AGND
RF
RF
IN
IN
B
A
Figure 4. LFCSP Pin Configuration
1
2
3
4
5
(Not to Scale)
DD
ADF4157
TOP VIEW
/2 and an equivalent input
PIN 1
INDICATOR
DD
DD
. In systems where V
DD
must have the same voltage as
must have the same voltage as
15 MUXOUT
14 LE
13 DATA
12 CLK
11 CE
DD
is 3 V, it can