ADF4157 AD [Analog Devices], ADF4157 Datasheet - Page 13

• Manufacturer Part Number: ADF4157
• Description: High Resolution 6 GHz Fractional-N Frequency Synthesizer
• Manufacturer: AD [Analog Devices]

R DIVIDER REGISTER (R2) MAP
With R1[2, 1, 0] set to [0, 1, 0], the on-chip R divider register is
programmed as shown in Figure 19.
CSR Enable
Setting this bit to 1 enables cycle slip reduction. This is a
method for improving lock times. Note that the signal at the PFD
must have a 50% duty cycle in order for cycle slip reduction to
work. In addition, the charge pump current setting must be set
to a minimum. See the Cycle Slip Reduction for Faster Lock
Times section for more information.
Note also that the cycle slip reduction feature can only be
operated when the phase detector polarity setting is positive
(DB6 in Register R3). It cannot be used if the phase detector
polarity is set to negative.
Charge Pump Current Setting
DB[27], DB[26], DB[25], and DB[24] set the charge pump
current setting. This should be set to the charge pump current
that the loop filter is designed with (see Figure 19).
Prescaler (P/P + 1)
The dual-modulus prescaler (P/P + 1), along with the INT,
FRAC, and MOD counters, determines the overall division ratio
from the RF
Operating at CML levels, it takes the clock from the RF input
stage and divides it down for the counters. It is based on
a synchronous 4/5 core. When set to 4/5, the maximum RF
frequency allowed is 3 GHz. Therefore, when operating
the ADF4157 above 3 GHz, the prescaler must be set to 8/9.
The prescaler limits the INT value.
IN
to the PFD input.
Rev. 0 | Page 13 of 20
RDIV2
Setting this bit to 1 inserts a divide-by-2 toggle flip flop between
the R counter and the PFD. This can be used to provide a 50%
duty cycle signal at the PFD for use with cycle slip reduction.
Reference Doubler
Setting DB[20] to 0 feeds the REF
RF R counter, disabling the doubler. Setting this bit to 1
multiplies the REF
into the 5-bit R counter. When the doubler is disabled,
the REF
the fractional synthesizer. When the doubler is enabled, both
the rising edge and falling edge of REF
the PFD input.
The maximum allowed REF
enabled is 30 MHz.
5-Bit R Counter
The 5-bit R counter allows the input reference frequency
(REF
the phase frequency detector (PFD). Division ratios from
1 to 32 are allowed.
Reserved Bits
All reserved bits should be set to 0 for normal operation.
With P = 4/5, N
With P = 8/9, N
IN
) to be divided down to produce the reference clock to
IN
falling edge is the active edge at the PFD input to
IN
MIN
MIN
frequency by a factor of 2 before feeding
= 23.
= 75.
IN
frequency when the doubler is
IN
signal directly to the 5-bit
IN
become active edges at
ADF4157