ADF4157 AD [Analog Devices], ADF4157 Datasheet - Page 8

• Manufacturer Part Number: ADF4157
• Description: High Resolution 6 GHz Fractional-N Frequency Synthesizer
• Manufacturer: AD [Analog Devices]

ADF4157
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 11. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REF
on power-down.
RF INPUT STAGE
The RF input stage is shown in Figure 12. It is followed by
a 2-stage limiting amplifier to generate the current-mode logic
(CML) clock levels needed for the prescaler.
RF INT DIVIDER
The RF INT counter allows a division ratio in the PLL feedback
counter. Division ratios from 23 to 4095 are allowed.
25-BIT FIXED MODULUS
The ADF4157 has a 25-bit fixed modulus. This allows output
frequencies to be spaced with a resolution of
where f
(PFD). For example, with a PFD frequency of 10 MHz,
frequency steps of 0.298 Hz are possible.
RF
RF
f
RES
IN
IN
A
B
PFD
= f
is the frequency of the phase frequency detector
REF
PFD
/2
IN
25
NC
GENERATOR
POWER-DOWN
Figure 11. Reference Input Stage
SW1
CONTROL
BIAS
Figure 12. RF Input Stage
NC
NC
SW3
SW2
2kΩ
100kΩ
1.6V
BUFFER
2kΩ
TO R COUNTER
AGND
AV
DD
IN
pin
Rev. 0 | Page 8 of 20
INT, FRAC, AND R RELATIONSHIP
The INT and FRAC values, in conjunction with the R counter,
make it possible to generate output frequencies that are spaced
by fractions of the phase frequency detector (PFD). See the
Synthesizer: A Worked Example section for more information.
The RF VCO frequency (RF
where:
RF
oscillator (VCO).
INT is the preset divide ratio of the binary 12-bit counter (23 to
4095).
FRAC is the numerator of the fractional division (0 to 2
where:
REF
D is the REF
R is the preset divide ratio of the binary 5-bit programmable
reference counter (1 to 32).
T is the REF
RF R COUNTER
The 5-bit RF R counter allows the input reference frequency
(REF
the PFD. Division ratios from 1 to 32 are allowed.
OUT
INPUT STAGE
IN
RF
f
FROM RF
IN
PFD
is the output frequency of the external voltage controlled
is the reference input frequency.
) to be divided down to produce the reference clock to
OUT
= REF
= f
IN
IN
PFD
divide-by-2 bit (0 or 1).
doubler bit.
IN
RF N DIVIDER
× (INT + (FRAC/2
× [(1 + D)/(R × (1+T))]
N-COUNTER
REG
INT
Figure 13. RF N Divider
OUT
) equation is
MOD
REG
25
N = INT + FRAC/MOD
INTERPOLATOR
THIRD-ORDER
))
FRACTIONAL
VALUE
FRAC
TO PFD
25
− 1).
RF
(1)
(2)