74lv161db NXP Semiconductors, 74lv161db Datasheet - Page 2

• Manufacturer Part Number: 74lv161db
• Description: Presettable Synchronous 4-bit Binary Counter; Asynchronous Reset
• Manufacturer: NXP Semiconductors

1. C
Philips Semiconductors
FEATURES
QUICK REFERENCE DATA
GND = 0 V; T
NOTES:
ORDERING INFORMATION
t
f
C
C
16-Pin Plastic DIL
16-Pin Plastic SO
16-Pin Plastic SSOP Type II
16-Pin Plastic TSSOP Type I
1997 May 15
PHL
max
SYMBOL
Optimized for low voltage applications: 1.0 to 3.6 V
Accepts TTL input levels between V
Typical V
T
Typical V
T
Asynchronous reset
Synchronous counting and loading
Two count enable inputs for n-bit cascading
Positive-edge triggered clock
Output capability: standard
I
Presettable synchronous 4-bit binary counter;
asynchronous reset
I
PD
CC
P
f
f
amb
amb
i
o
PD
D
= input frequency in MHz; C
/t
= output frequency in MHz; V
(C
category: MSI
PLH
= C
= 25 C
= 25 C
L
is used to determine the dynamic power dissipation (P
PD
OLP
OHV
V
PACKAGES
amb
CC
Propagation delay
CP to Q
CP to TC
MR to Q
MR to TC
CET to TC
Maximum clock frequency
Input capacitance
Power dissipation capacitance per gate
(output ground bounce) < 0.8 V at V
(output V
V
2
= 25 C; t
CC
2
f
o
n
n
) = sum of the outputs.
OH
f
i
r
) (C
= t
undershoot) > 2 V at V
PARAMETER
f
2.5 ns
L
L
= output load capacity in pF;
CC
CC
= supply voltage in V;
V
TEMPERATURE RANGE
CC
= 2.7 V and V
2
–40 C to +125 C
–40 C to +125 C
–40 C to +125 C
–40 C to +125 C
f
o
) where:
CC
CC
= 3.3 V,
= 3.3 V,
CC
= 3.6 V
C
V
V
D
L
CC
I
= GND to V
= 15 pF;
in W)
= 3.3 V
OUTSIDE NORTH AMERICA
2
CONDITIONS
DESCRIPTION
The 74LV161 is a low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT161.
The 74LV161 is a synchronous presettable binary counter which
features an internal look-head carry and can be used for high-speed
counting. Synchronous operation is provided by having all flip-flops
clocked simultaneously on the positive-going edge of the clock (CP).
The outputs (Q
LOW level. A LOW level at the parallel enable input (PE) disables the
counting action and causes the data at the data inputs (D
loaded into the counter on the positive-going edge of the clock
(providing that the set-up and hold time requirements for PE are met).
Preset takes place regardless of the levels at count enable inputs
(CEP and CET). A low level at the master reset input (MR) sets all
four outputs of the flip-flops (Q
levels at CP, PE, CET and CEP inputs (thus providing an
asynchronous clear function).
The look-ahead carry simplifies serial cascading of the counters.
Both count enable inputs (CEP and CET) must be HIGH to count.
The CET input is fed forward to enable the terminal count output
(TC). The TC output thus enabled will produce a HIGH output pulse
of a duration approximately equal to a HIGH level output of Q
pulse can be used to enable the next cascading stage. The
maximum clock frequency for the cascaded counters is determined
by the CP to TC propagation delay and CEP to CP set-up time,
according to the following formula:
CC
f
max
74LV161 DB
74LV161 PW
1
74LV161 N
74LV161 D
+
tp
(max)
0
(CP to TC) ) t
to Q
3
) of the counters may be preset to a HIGH or
1
NORTH AMERICA
74LV161PW DH
0
74LV161 DB
74LV161 N
74LV161 D
su
to Q
TYPICAL
(CEP to CP)
3
3.5
15
18
15
17
77
25
) to LOW level regardless of the
9
Product specification
74LV161
853–1917 18039
PKG. DWG. #
SOT109-1
SOT338-1
SOT403-1
SOT38-4
0
to D
UNIT
MHz
pF
pF
ns
3
0
) to be
. This