74lv574db NXP Semiconductors, 74lv574db Datasheet - Page 7

• Manufacturer Part Number: 74lv574db
• Description: Octal D-type Flip-flop; Positive Edge-trigger 3-state
• Manufacturer: NXP Semiconductors

Philips Semiconductors
AC WAVEFORMS
V
V
V
output load.
V
V
V
V
1998 Jun 10
M
M
OL
X
X
Y
Y
HIGH-to-OFF
OFF-to-HIGH
OFF-to-LOW
Figure 1. Clock (CP) to output (Qn) propagation delays, the
LOW-to-OFF
Octal D-type flip-flop; positive edge-trigger (3-State)
= V
= V
= V
= V
clock pulse (CP) and the maximum clock pulse frequency
= 1.5V at V
= 0.5 * V
OE INPUT
Q
and V
OUTPUT
OUTPUT
CP INPUT
n
OL
OL
OH
OH
OUTPUT
V
GND
GND
V
V
V
V
OH
OL
+ 0.3V at V
+ 0.1V
GND
CC
OH
– 0.3V at V
– 0.1V
OL
OH
V
I
Figure 2. 3-state enable and disable times
V
CC
I
are the typical output voltage drop that occur with the
CC
at V
CC
CC
w 2.7V and v 3.6V
CC
at V
at V
enabled
outputs
CC
CC
t
V
PLZ
V
t
t 2.7V and w 4.5V
M
PHZ
CC
M
CC
w 2.7V and v 3.6V
t
w 2.7V and v 3.6V
PHL
t
W
2.7V and w 4.5V
2.7V and w 4.5V
V
1/f
V
X
M
V
max
Y
disabled
outputs
t
PZL
t
PZH
t
PLH
V
SV00718
M
outputs
enabled
SV00344
V
M
7
NOTE:
The shaded areas indicate when the input is permitted to change for
predictable output performance.
TEST CIRCUIT
Figure 3.
Q
NOTE: the shaded areas indicate when the input is permitted to change
for predictable output performance.
n
CP INPUT
D
OUTPUT
n
GENERATOR
SWITCH POSITION
t
t
t
INPUT
PLH/
PLZ/
PHZ/
TEST
DEFINITIONS
R
C
R
GND
GND
PULSE
V
V
L
L
T
OH
OL
t
t
= Load resistor
= Load capacitance includes jig and probe capacitiance.
t
V
V
= Termination resistance should be equal to Z
PZL
Ï Ï Ï Ï
Ï Ï Ï Ï
Ï Ï Ï Ï
PHL
PZH
Figure 4.
I
I
Data set-up and hold times for the Dn input to the CP
2 * V
Open
GND
S
CC
Test Circuit for Outputs
1
V
V
M
I
Load circuitry for switching times
(1)
R
T
V
M
t
su
Ï Ï Ï Ï Ï Ï
Ï Ï Ï Ï Ï Ï
Ï Ï Ï Ï Ï Ï
input
D.U.T.
w 4.5V
V
2.7–3.6V
CC
< 2.7V
t
h
V
CC
V
V
O
M
C
OUT
V
2.7V
V
L
V
CC
CC
I
Product specification
of pulse generators.
74LV574
50 pF
t
su
SV00896
Ï Ï Ï Ï
Ï Ï
R
R
SV00345
L
L
= 1k
= 1k
t
2 * V
h
Open
GND
CC