74lv573db NXP Semiconductors, 74lv573db Datasheet - Page 2

• Manufacturer Part Number: 74lv573db
• Description: Octal D-type Transparent Latch 3-state
• Manufacturer: NXP Semiconductors

1. C
2. The condition is V
Philips Semiconductors
FEATURES
QUICK REFERENCE DATA
GND = 0V; T
NOTES:
ORDERING AND PACKAGE INFORMATION
PIN DESCRIPTION
t
C
C
20-Pin Plastic DIL
20-Pin Plastic SO
20-Pin Plastic SSOP Type II
20-Pin Plastic TSSOP Type I
PIN NUMBER
1
2, 3, 4, 5,
6, 7, 8, 9
19, 18, 17, 16,
15, 14, 13, 12
10
11
20
1998 Jun 10
PHL
Wide operating voltage: 1.0 to 5.5V
Optimized for Low Voltage applications: 1.0V to 3.6V
Accepts TTL input levels between V
Typical V
T
Typical V
T
Inputs and outputs on opposite sides of package allowing easy
interface with microprocessors
Useful as input or output port for microprocessors/microcomputer
Common 3-State output enable input
Output capability: bus driver
I
Octal D-type transparent latch (3-State)
I
PD
CC
P
f
f
amb
amb
i
o
PD
D
= input frequency in MHz; C
/t
= output frequency in MHz; V
(C
category: MSI
PLH
= C
SYMBOL
= 25 C
= 25 C
L
is used to determine the dynamic power dissipation (P
PACKAGES
PD
OLP
OHV
amb
V
CC
(output ground bounce) < 0.8V at V
(output V
V
2
= 25 C; t
CC
SYMBOL
OE
D0–D7
Q0–Q7
GND
LE
VCC
2
f
I
o
x f
= GND to V
) = sum of the outputs.
i
OH
r
Propagation delay
Dn to Qn
LE to Qn
Input capacitance
Power dissipation capacitance per latch
) (C
= t
undershoot) > 2V at V
f
v2.5 ns
FUNCTION
Output enabled input (active LOW)
Data inputs
Data outputs
Ground (0V)
Latch enable input (active HIGH)
Positive supply voltage
TEMPERATURE RANGE
L
L
CC.
= output load capacity in pF;
CC
–40 C to +125 C
–40 C to +125 C
–40 C to +125 C
–40 C to +125 C
V
CC
= supply voltage in V;
CC
PARAMETER
= 2.7V and V
2
f
o
) where:
CC
CC
= 3.3V,
= 3.3V,
CC
= 3.6V
D
OUTSIDE NORTH
in W)
74LV573 PW
74LV573 DB
74LV573 N
74LV573 D
AMERICA
C
V
Notes 1, 2
L
CC
2
= 15pF
= 3.3V
DESCRIPTION
The 74LV573 is a low-voltage Si-gate CMOS device that is pin and
function compatible with 74HC/HCT573.
The 74LV573 is an octal D-type transparent latch featuring separate
D-type inputs for each latch and 3-State outputs for bus oriented
applications. A latch enable (LE) input and an output enable (OE)
input are common to all internal latches.
The ‘573’ consists of eight D-type transparent latches with 3-State
true outputs. When LE is HIGH, data at the D
latches. In this condition the latches are transparent, i.e., a latch
output will change each time its corresponding D-input changes.
When LE is LOW the latches store the information that was present
at the D-inputs a set-up time preceding the HIGH-to-LOW transition
of LE. When OE is LOW, the contents of the eight latches are
available at the outputs. When OE is HIGH, the outputs go to the
high impedance OFF-state. Operation of the OE input does not
affect the state of the latches.
The ‘573’ is functionally identical to the ‘563’ and the ‘373’, but the
‘563’ has inverted outputs and the ‘373’ has a different pin
arrangement.
CONDITIONS
NORTH AMERICA
74LV573PW DH
74LV573 DB
74LV573 N
74LV573 D
TYPICAL
3.5
12
13
26
n
Product specification
inputs enters the
PKG. DWG. #
SOT146-1
SOT163-1
SOT339-1
SOT360-1
74LV573
853-1989 19545
UNIT
pF
pF
ns