pcf8532 NXP Semiconductors, pcf8532 Datasheet - Page 19

• Manufacturer Part Number: pcf8532
• Description: Universal Lcd Driver For Low Multiplex Rates
• Manufacturer: NXP Semiconductors

NXP Semiconductors
PCF8532_1
Product data sheet
7.16.1 Bit transfer
7.16.2 START and STOP conditions
7.16.3 System configuration
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as a control signal. Bit transfer is shown in
Both data and clock lines remain HIGH when the bus is not busy.
A HIGH-to-LOW change of the data line, while the clock is HIGH is defined as the START
condition (S).
A LOW-to-HIGH change of the data line while the clock is HIGH is defined as the STOP
condition (P).
The START and STOP conditions are shown in
A device generating a message is a transmitter, a device receiving a message is the
receiver. The device that controls the message is the master and the devices which are
controlled by the master are the slaves. The system configuration is shown in
Fig 11. Bit transfer
Fig 12. Definition of START and STOP conditions
Fig 13. System configuration
SCL
SDA
SDA
SCL
TRANSMITTER/
RECEIVER
MASTER
START condition
SDA
SCL
S
Rev. 1 — 10 February 2009
RECEIVER
SLAVE
data valid
data line
stable;
TRANSMITTER/
RECEIVER
Universal LCD driver for low multiplex rates
SLAVE
change
allowed
of data
Figure
12.
TRANSMITTER
MASTER
Figure
STOP condition
mba607
P
11.
PCF8532
TRANSMITTER/
© NXP B.V. 2009. All rights reserved.
RECEIVER
MASTER
Figure
mbc622
mga807
SDA
SCL
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13.