pcf85162 NXP Semiconductors, pcf85162 Datasheet - Page 16

• Manufacturer Part Number: pcf85162
• Description: Universal Lcd Driver For Low Multiplex Rates
• Manufacturer: NXP Semiconductors

NXP Semiconductors
PCF85162_1
Product data sheet
7.12 Subaddress counter
7.11 Data pointer
The following applies to
The addressing mechanism for the display RAM is realized using the data pointer. This
allows the loading of an individual display data byte, or a series of display data bytes, into
any location of the display RAM. The sequence commences with the initialization of the
data pointer by the load-data-pointer command (see
an arriving data byte is stored at the display RAM address indicated by the data pointer.
The filling order is shown in
pointer is automatically incremented by a value dependent on the selected LCD drive
mode:
If an I
Consequently, the data pointer must be rewritten prior to further RAM accesses.
The storage of display data is conditioned by the content of the subaddress counter.
Storage is allowed only when the content of the subaddress counter matches with the
hardware subaddress applied to A0, A1, and A2. The subaddress counter value is defined
by the device-select command (see
and the hardware subaddress do not match, then data storage is inhibited but the data
pointer is incremented as if data storage had taken place. The subaddress counter is also
incremented when the data pointer overflows.
In cascaded applications each PCF85162 in the cascade must be addressed separately.
Initially, the first PCF85162 is selected by sending the device-select command matching
the first device's hardware subaddress. Then the data pointer is set to the preferred
display RAM address by sending the load-data-pointer command.
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In static drive mode the eight transmitted data bits are placed in row 0 of eight
successive 4-bit RAM words.
In 1:2 multiplex mode the eight transmitted data bits are placed in pairs into
row 0 and 1 of four successive 4-bit RAM words.
In 1:3 multiplex mode the eight bits are placed in triples into row 0, 1, and 2 of three
successive 4-bit RAM words, with bit 3 of the third address left unchanged. It is not
recommended to use this bit in a display because of the difficult addressing. This last
bit may, if necessary, be controlled by an additional transfer to this address but care
should be taken to avoid overwriting adjacent data because always full bytes are
transmitted.
In the 1:4 multiplex mode, the eight transmitted data bits are placed in quadruples into
row 0, 1, 2, and 3 of two successive 4-bit RAM words.
In static drive mode by eight.
In 1:2 multiplex drive mode by four.
In 1:3 multiplex drive mode by three.
In 1:4 multiplex drive mode by two.
2
C-bus data access terminates early, the state of the data pointer is unknown.
Rev. 01 — 7 January 2010
Figure
Figure
10:
10. After each byte is stored, the content of the data
Table
12). If the content of the subaddress counter
Universal LCD driver for low multiplex rates
Table
11). Following this command,
PCF85162
© NXP B.V. 2010. All rights reserved.
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