pcf8583 NXP Semiconductors, pcf8583 Datasheet

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pcf8583

Manufacturer Part Number
pcf8583
Description
Clock/calendar With 240 X 8-bit Ram
Manufacturer
NXP Semiconductors
Datasheet

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Product specification
Supersedes data of 1997 Mar 28
File under Integrated Circuits, IC12
DATA SHEET
PCF8583
Clock/calendar with 240
RAM
INTEGRATED CIRCUITS
8-bit
1997 Jul 15

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pcf8583 Summary of contents

Page 1

... DATA SHEET PCF8583 Clock/calendar with 240 RAM Product specification Supersedes data of 1997 Mar 28 File under Integrated Circuits, IC12 INTEGRATED CIRCUITS 8-bit 1997 Jul 15 ...

Page 2

... Method 1: fixed osci capacitor 14.1.2 Method 2: OSCI Trimmer 14.1.3 Method 3: 15 PACKAGE OUTLINES 16 SOLDERING 16.1 Introduction 16.2 DIP 16.2.1 Soldering by dipping or by wave 16.2.2 Repairing soldered joints 16.3 SO 16.3.1 Reflow soldering 16.3.2 Wave soldering 16.3.3 Repairing soldered joints 17 DEFINITIONS 2 C-BUS 18 LIFE SUPPORT APPLICATIONS 19 PURCHASE OF PHILIPS I 2 Product specification PCF8583 2 C COMPONENTS ...

Page 3

... Jul 15 8-bit RAM 2 GENERAL DESCRIPTION The PCF8583 is a clock/calendar circuit based on a 2048-bit static CMOS RAM organized as 256 words by 8 bits. Addresses and data are transferred serially via the two-line bidirectional I register is incremented automatically after each written or read data byte ...

Page 4

... Product specification PCF8583 control/status 00 01 hundredth of a second seconds minutes hours year/date weekdays/months 07 timer alarm control 08 alarm registers or RAM 0F RAM (240 8) FF MRB001 OSCI OSCO 2 7 INT PCF8583P PCF8583T SCL 4 5 SDA V SS MRB014 Fig.2 Pinning diagram. ...

Page 5

... Philips Semiconductors Clock/calendar with 240 7 FUNCTIONAL DESCRIPTION The PCF8583 contains a 256 by 8-bit RAM with an 8-bit auto-increment address register, an on-chip 32.768 kHz oscillator circuit, a frequency divider, a serial two-line 2 bidirectional I C-bus interface and a power-on reset circuit. The first 16 bytes of the RAM (memory addresses 00 to 0F) are designed as addressable 8-bit parallel special function registers ...

Page 6

... RAM LSB Fig.3 Control/status register. 6 Product specification PCF8583 memory location 00 reset state: 0000 0000 timer flag (50% duty factor seconds flag if alarm enable bit is 0) alarm flag (50% duty factor minutes flag if alarm enable bit is 0) alarm enable bit: ...

Page 7

... RAM CLOCK MODES Fig.4 Register arrangement. 7 Product specification control/status free 04 free 05 free 06 timer alarm control 08 alarm free 0C free 0D free 0E alarm timer 0F free RAM EVENT COUNTER MRB015 PCF8583 ...

Page 8

... BCD ten days ( binary) year ( binary, read the mask flag is set) memory location 06 (weekdays/months) reset state: 0000 0001 unit months BCD ten months weekdays ( binary, read the mask flag is set) PCF8583 ...

Page 9

... Fig.9). Remark: In the 12 h mode, bits 6 and 7 of the alarm hours register must be the same as the hours counter. 9 Product specification PCF8583 CONTENTS OF THE MONTH COUNTER and and 11 2, year = 0 ...

Page 10

... Product specification PCF8583 ...

Page 11

... These conditions are clock alarm, timer alarm, timer overflow, and event counter alarm. An interrupt occurs when the alarm flag or the timer flag is set, and the corresponding interrupt is enabled. In all events, the interrupt is cleared only by software resetting of the flag which initiated the interrupt. 11 Product specification Interrupt output PCF8583 ...

Page 12

... Initialization 2 C-bus interface, the Product specification PCF8583 ...

Page 13

... CLOCK/CALENDAR ALARM alarm timer control alarm (1) alarm timer overflow interrupt interrupt Fig.11 Alarm and timer interrupt logic diagram. 13 Product specification oscillator TIMER timer overflow control ALARM CONTROL REGISTER INT MBD818 PCF8583 ...

Page 14

... HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop condition (P). SDA SCL START condition 1997 Jul 15 8-bit RAM 2 C-BUS data line change stable; of data data valid allowed Fig.12 Bit transfer. S Fig.13 Definition of start and stop conditions. 14 Product specification PCF8583 MBC621 SDA SCL P STOP condition MBC622 ...

Page 15

... In this event the transmitter must leave the data line HIGH to enable the master to generate a stop condition START CONDITION Fig.15 Acknowledgment on the I 15 Product specification PCF8583 MASTER MASTER TRANSMITTER / TRANSMITTER RECEIVER MBA605 not acknowledge acknowledge 8 9 clock pulse for ...

Page 16

... DD SS handbook, halfpage 9.2 Clock/calendar READ/WRITE cycles 2 The I C-bus configuration for the different PCF8583 READ and WRITE cycles is shown in Figs 17, 18 and 19. handbook, full pagewidth S SLAVE ADDRESS Fig.17 Master transmits to slave receiver (WRITE) mode. 1997 Jul 15 8-bit RAM 2 C-bus, the device which should respond is addressed first ...

Page 17

... Product specification acknowledgement acknowledgement from slave from master DATA bytes R/W auto increment memory word address no acknowledgement DATA last byte auto increment MBD823 memory word address acknowledgement from slave A DATA 1 P last bytes auto increment word address MBD824 PCF8583 from master P 1 ...

Page 18

... V SCL Hz OSCI amb amb note 4 note 5 note 0 note 6 18 Product specification PCF8583 MIN. MAX. UNIT 0 300 + +150 ...

Page 19

... V until stable operation of the oscillator is established. DD < handbook, halfpage I DDO ( Product specification (1) MIN. TYP. 250 +250 input current may flow; this current SS MRB012 (V) DD PCF8583 MAX. UNIT ...

Page 20

... Jul 15 8-bit RAM = 40 to +85 C; unless otherwise specified. CONDITIONS for V = 100 mV 1.5 V amb DD note C-bus specification, with applications, is given in brochure “The I 20 Product specification PCF8583 MIN. TYP. MAX 100 100 4.7 4.7 4.0 4.7 4.0 1.0 ...

Page 21

... Initialization (alarm functions). Routine: Set clock to time T and set alarm to time time T 14.1.3 Direct measurement of OSC out (accounting for test probe capacitance). The PCF8583 slave address has a fixed combination 1010 as group 1. 2 C-bus) a signal faster 21 Product specification PCF8583 BIT 0 ACKNOWLEDGE STOP ...

Page 22

... CALENDAR OSCI PCF8583 '1010' SDA OSCO EVENT SCL COUNTER OSCI PCF8583 '1010' SDA OSCO V SS SDA SCL 2 (I C-bus) Fig.22 Application diagram. 22 Product specification V DD SDA MASTER TRANSMITTER SCL pull-up resistor rise / C-bus MRB018 PCF8583 ...

Page 23

... scale ( 0.53 1.07 0.36 9.8 0.38 0.89 0.23 9.2 0.021 0.042 0.014 0.39 0.015 0.035 0.009 0.36 REFERENCES JEDEC EIAJ MO-001AN ( 6.48 3.60 8.25 2.54 7.62 6.20 3.05 7.80 0.26 0.14 0.32 0.10 0.30 0.24 0.12 0.31 EUROPEAN PROJECTION Product specification PCF8583 SOT97-1 ( max. 10.0 0.254 1.15 8.3 0.39 0.01 0.045 0.33 ISSUE DATE 92-11-17 95-02-04 ...

Page 24

... REFERENCES JEDEC EIAJ detail 1.1 1.1 1.45 0.25 0.25 0.45 1.0 0.043 0.043 0.057 0.01 0.01 0.018 0.039 EUROPEAN PROJECTION Product specification PCF8583 SOT176 (1) Z 2.0 0.1 1 0.079 0.004 0.071 ISSUE DATE 95-02-25 97-05-22 ...

Page 25

... Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds 300 C. When using a dedicated tool, all other leads can be soldered in one operation within seconds between 270 and 320 C. 25 Product specification PCF8583 ...

Page 26

... Philips. This specification can be ordered using the code 9398 393 40011. 1997 Jul 15 8-bit RAM C COMPONENTS 2 C components conveys a license under the Philips’ system provided the system conforms to the I 26 Product specification PCF8583 2 C patent to use the 2 C specification defined by ...

Page 27

... Philips Semiconductors Clock/calendar with 240 1997 Jul 15 8-bit RAM NOTES 27 Product specification PCF8583 ...

Page 28

Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 160 1010, ...

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