pcf8812 NXP Semiconductors, pcf8812 Datasheet - Page 6

• Manufacturer Part Number: pcf8812
• Description: 65 X 102 Pixels Matrix Lcd Driver
• Manufacturer: NXP Semiconductors

Philips Semiconductors
7.1.8
TEST1, TEST3, TEST4 and TEST5 must be connected
to V
user.
7.1.9
Serial data input line.
7.1.10
Input for the clock signal 0 to 4 Mbit/s.
7.1.11
Input to select either command/address or data input.
7.1.12
The enable pin allows data to be clocked in; the signal is
active LOW.
7.1.13
When the on-chip oscillator is used this input must be
connected to V
connected to this input. If the oscillator and external clock
are both inhibited by connecting the OSC pin to V
display is not clocked and may be left in a DC state.
To avoid this the chip should always be put into
Power-down mode before stopping the clock.
7.1.14
This signal will reset the device and must be applied to
properly initialize the chip; the signal is active LOW.
8
8.1
The on-chip oscillator provides the clock signal for the
display system. No external components are required and
the OSC input must be connected to V
clock signal, if used, is connected to this input.
8.2
The address counter assigns addresses to the display
data RAM for writing. The X address X6 to X0 and the
Y address Y3 to Y0 are set separately. After a write
operation the address counter is automatically
incremented by 1 according to the V flag (see Chapter 9).
2004 Feb 23
65
SS
FUNCTIONAL DESCRIPTION
, TEST2 must be left open-circuit. Not accessible to
Oscillator
Address Counter (AC)
TEST1
SDIN:
SCLK:
D/C:
SCE:
OSC:
RES:
102 pixels matrix LCD driver
MODE SELECT
CHIP ENABLE
RESET
DD
OSCILLATOR
SERIAL DATA LINE
SERIAL CLOCK LINE
TO
. An external clock signal, if used, is
TEST5:
TEST PADS
DD
. An external
SS
the
6
8.3
The PCF8812 contains a 65
stores the display data. The RAM is divided into 8 banks of
102 bytes (8
(1
the RAM via the serial interface. There is a direct
correspondence between the X address and the column
output number.
8.4
The timing generator produces the various signals
required to drive the internal circuitry. Internal chip
operation is not affected by operations on the data buses.
8.5
The display is generated by continuously shifting rows of
RAM data to the dot matrix LCD via the column outputs.
The display status (all dots on/off and normal/inverse
video) is set by bits E and D in the command ‘display
control’ (see Table 2).
8.6
The PCF8812 contains 65 row and 102 column drivers,
which connect the appropriate LCD bias voltages in
sequence to the display in accordance with the data to be
displayed. Figure 2 shows typical waveforms. Unused
outputs should be left unconnected.
102 bits). During RAM access, data is transferred to
Display Data RAM (DDRAM)
Timing generator
Display address counter
LCD row and column drivers
8
102 bits) and one bank of 102 bits
102 bit static RAM which
Product specification
PCF8812