pcf8833 NXP Semiconductors, pcf8833 Datasheet - Page 43

• Manufacturer Part Number: pcf8833
• Description: Stn Rgb - 132 X 132 X 3 Driver
• Manufacturer: NXP Semiconductors

Philips Semiconductors
6.2.27
The display data RAM access conditions can be defined by using the Memory data access control (MADCTL) command.
The used single control bits together with their reset states are given in Table 41.
Table 40 Memory data access control register bits
Note
1. Refer to Section 6.2.24.4 for an explanation of LAO on scroll modes and to Section 6.2.23 for an explanation of LAO
Table 41 Explanation of the memory data access control bits
The relationship between RAM and display for the MX, MY, RGB and LAO control bits is illustrated Fig.22.
Combinations of MX, MY and V are described in more detail in Section 7.2.
2003 Feb 14
handbook, full pagewidth
MY
MX
V
LAO
RGB
STN RGB - 132
D/C
on Partial mode.
BIT
0
1
M
EMORY DATA ACCESS CONTROL
no mirror Y
no mirror X
RAM write in X direction
line address order (top to bottom)
RGB
MY
7
0
LOGIC 0 (RESET STATE)
MX
interface
6
0
132
D7 = 0
131
0
1
2
Fig.22 Display data RAM access control.
3 driver
V
5
1
D7 = 1
D6 = 0
D6 = 1
131
2
1
0
131
0 1 2
0,0
LAO
D3 = 0:RGB
D3 = 1:BGR
4
1
column address
column drivers
(1)
RAM
43
RGB
2
MGU931
3
0
131
1
mirror Y
mirror X
vertical RAM write; in Y direction
line address order (bottom to top)
BGR
0
D4 = 0
131
0
1
2
X
2
1
D4 = 1
131
2
1
0
DISPLAY
LOGIC 1
X
1
1
Objective specification
X
0
0
PCF8833
DEFAULT
36H
00H