pca8565 NXP Semiconductors, pca8565 Datasheet - Page 11
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pca8565
Manufacturer Part Number
pca8565
Description
Real Time Clock/calender
Manufacturer
NXP Semiconductors
Datasheet
1.PCA8565.pdf
(26 pages)
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Philips Semiconductors
9. Characteristics of the I
9397 750 10695
Product data
Fig 5. POR override sequence.
handbook, full pagewidth
SDA
SCL
power up
8.8 Power-On Reset (POR) override
9.1 Bit transfer
8 ms
Repeat 7 and 8 for additional increments.
The POR duration is directly related to the crystal oscillator start-up time. Due to the
long start-up times experienced by these types of circuits, a mechanism has been
built in to disable the POR and hence speed up on-board test of the device. The
setting of this mode requires that the I
specific order as shown in
Once the override mode has been entered, the device immediately stops being reset
and normal operation may commence i.e. entry into the EXT_CLK test mode via
I
TESTC must be set to logic 1 before re-entry into the override mode is possible.
Setting TESTC to logic 0 during normal operation has no effect except to prevent
entry into the POR override mode.
The I
modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both
lines must be connected to a positive supply via a pull-up resistor. Data transfer may
be initiated only when the bus is not busy.
One data bit is transferred during each clock pulse. The data on the SDA line must
remain stable during the HIGH period of the clock pulse as changes in the data line at
this time will be interpreted as a control signal (see
2
3. Clear STOP (control/status 1, bit STOP = 0)
4. Set time registers to desired value
5. Apply 32 clock pulses to CLKOUT
6. Read time registers to see the first change
7. Apply 64 clock pulses to CLKOUT
8. Read time registers to see the second change.
C-bus access. The override mode may be cleared by writing a logic 0 to TESTC.
2
C-bus is for bidirectional, two-line communication between different ICs or
500 ns
2
C-bus
Rev. 01 — 31 March 2003
2000 ns
Figure
5. All timings are required minimums.
2
C-bus pins, SDA and SCL, be toggled in a
Figure
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
override active
6).
Real time clock/calender
PCA8565
MGM664
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