m41st85w STMicroelectronics, m41st85w Datasheet - Page 17

• Manufacturer Part Number: m41st85w
• Description: 3.0/3.3v I 2c Combination Serial Rtc, Nvram Supervisor And Microprocessor Supervisor
• Manufacturer: STMicroelectronics

2.3
Figure 12. Write mode sequence
2.4
Note:
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
Write mode
In this mode the master transmitter transmits to the M41ST85W slave receiver. Bus protocol
is shown in
is placed on the bus and indicates to the addressed device that word address An will follow
and is to be written to the on-chip address pointer. The data word to be written to the
memory is strobed in next and the internal address pointer is incremented to the next
memory location within the RAM on the reception of an acknowledge clock. The M41ST85W
slave receiver will send an acknowledge clock to the master transmitter after it has received
the slave address and again after it has received the word address and each data byte.
Data retention mode
With valid V
WRITE Cycles. Should the supply voltage decay, the M41ST85W will automatically
deselect, write protecting itself (and any external SRAM) when V
V
registers. At this time, the Reset pin (RST) is driven active and will remain active until V
returns to nominal levels. External RAM access is inhibited in a similar manner by forcing
E
long as V
Back-up Switchover Voltage (V
SNAPHAT
attached battery supply.
All outputs become high impedance. The V
to the attached memory with less than 0.3 volts drop under this condition. On power up,
when V
The RST signal also remains active during this time (see
Most low power SRAMs on the market today can be used with the M41ST85W RTC
SUPERVISOR. There are, however some criteria which should be used in making the final
choice of an SRAM to use. The SRAM must be designed in a way where the chip enable
input disables all other inputs to the SRAM. This allows inputs to the M41ST85W and
SRAMs to be “Don’t Care” once V
guarantee data retention down to V
sufficient to meet the system needs with the chip enable output propagation delays
included. If the SRAM includes a second chip enable pin (E2), this pin should be tied to
V
OUT
PFD
CON
.
(max) and V
to a high level. This level is within 0.2 volts of the V
CC
S
CC
®
returns to a nominal value, write protection continues for t
ADDRESS
Figure
CC
battery, and the clock registers and external SRAM are maintained from the
remains at an out-of-tolerance condition. When V
SLAVE
applied, the M41ST85W can be accessed as described above with READ or
PFD
12. Following the START condition and slave address, a logic '0' (R/W=0)
(min). This is accomplished by internally inhibiting access to the clock
ADDRESS (An)
WORD
SO
), power input is switched from the V
CC
CC
falls below V
=2.0 volts. The chip enable access time must be
DATA n
OUT
pin is capable of supplying 100 µA of current
PFD
(min). The SRAM should also
DATA n+1
BAT
Figure 20 on page
. E
CON
CC
CC
falls below the Battery
will remain at this level as
falls between
rec
CC
DATA n+X
by inhibiting E
pin to the
AI00591
33).
P
CON
17/41
CC
.