m41st85w STMicroelectronics, m41st85w Datasheet - Page 32

• Manufacturer Part Number: m41st85w
• Description: 3.0/3.3v I 2c Combination Serial Rtc, Nvram Supervisor And Microprocessor Supervisor
• Manufacturer: STMicroelectronics

Figure 19. Bus timing requirements sequence
Table 12.
1. Valid for Ambient Operating Temperature: T
2. Transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling edge of SCL.
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t
Symbol
HD:DAT
t
t
t
t
SU:STO
HD:STA
t
SU:DAT
SU:STA
t
t
f
t
EXPD
HIGH
LOW
BUF
SCL
t
t
F
R
(2)
SDA
SCL
SCL Clock Frequency
Time the bus must be free before a new transmission can start
EX to E
SDA and SCL Fall Time
Data Hold Time
START Condition Hold Time (after this period the first clock pulse is generated)
Clock High Period
Clock Low Period
SDA and SCL Rise Time
Data Setup Time
START Condition Setup Time (only relevant for a repeated start condition)
STOP Condition Setup Time
AC characteristics
tBUF
CON
P
Propagation Delay
S
tHD:STA
tR
A
= –40 to 85°C; V
Parameter
tLOW
tHIGH
tF
(1)
CC
tHD:DAT
= 2.7 to 3.6V (except where otherwise noted).
tSU:DAT
SR
tSU:STA
tHD:STA
Min
600
600
100
600
600
1.3
1.3
0
0
P
AI00589
tSU:STO
Max
400
300
300
15
Unit
kHz
µs
ns
ns
µs
ns
ns
µs
ns
ns
ns
ns