x1205s8izt1 Intersil Corporation, x1205s8izt1 Datasheet

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x1205s8izt1

Manufacturer Part Number
x1205s8izt1
Description
2-wire? Rtc Real Time Clock/calendar
Manufacturer
Intersil Corporation
Datasheet
2-Wire™ RTC Real Time Clock/Calendar
FEATURES
• Real Time Clock/Calendar
• 2 Polled Alarms (Non-volatile)
• Oscillator Compensation on chip
• Battery Switch or Super Cap Input
• 2-Wire™ Interface interoperable with I2C*
• Low Power CMOS
• Small Package Options
• Repetitive Alarms
• Temperature Compensation
• Pb-Free Plus Anneal Available (RoHS Compliant)
APPLICATIONS
• Utility Meters
• HVAC Equipment
BLOCK DIAGRAM
—Tracks time in Hours, Minutes, and Seconds
—Day of the Week, Day, Month, and Year
—Settable on the Second, Minute, Hour, Day of
—Repeat Mode (periodic interrupts)
—Internal feedback resistor and compensation
—64 position Digitally Controlled Trim Capacitor
—6 digital frequency adjustment settings to
—400kHz data transfer rate
—1.25µA Operating Current (Typical)
—8-Lead SOIC and 8-Lead TSSOP
the Week, Day, or Month
capacitors
±30ppm
SCL
SDA
32.768kHz
Interface
Decoder
Serial
IRQ
X1
X2
®
1
8
Decode
Control
Logic
Data Sheet
(EEPROM)
Registers
Control
Interrupt Enable
Oscillator
Compensation
1-888-INTERSIL or 1-888-468-3774
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
OSC
Alarm
Registers
Frequency
(SRAM)
Status
• Audio/Video Components
• Set Top Box/Television
• Modems
• Network Routers, Hubs, Switches, Bridges
• Cellular Infrastructure Equipment
• Fixed Broadband Wireless Equipment
• Pagers/PDA
• POS Equipment
• Test Meters/Fixtures
• Office Automation (Copiers, Fax)
• Home Appliances
• Computer Products
• Other Industrial/Medical/Automotive
DESCRIPTION
The X1205 device is a Real Time Clock with
clock/calendar,
compensation, and battery backup switch.
The oscillator uses an external, low-cost 32.768kHz
crystal. All compensation and trim components are
integrated on the chip. This eliminates several external
discrete components and a trim capacitor, saving
board area and component cost.
The Real-Time Clock keeps track of time with
separate registers for Hours, Minutes, and Seconds.
The Calendar has separate registers for Date, Month,
Year and Day-of-week.
through 2099, with automatic leap year correction.
Divider
September 23, 2005
All other trademarks mentioned are the property of their respective owners.
|
1Hz
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Alarm
Alarm
Copyright Intersil Americas Inc. 2005. All Rights Reserved
two
Calendar
Timer
Logic
polled
The calendar is correct
Compare
Alarm Regs
(EEPROM)
Registers
(SRAM)
Keeping
alarms,
Time
X1205
FN8097.2
oscillator

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x1205s8izt1 Summary of contents

Page 1

Data Sheet 2-Wire™ RTC Real Time Clock/Calendar FEATURES • Real Time Clock/Calendar —Tracks time in Hours, Minutes, and Seconds —Day of the Week, Day, Month, and Year • 2 Polled Alarms (Non-volatile) —Settable on the Second, Minute, Hour, Day ...

Page 2

PIN DESCRIPTIONS X1 X2 IRQ internal connection Ordering Information PART NUMBER PART MARKING X1205S8* X1205 X1205S8Z* (Note) X1205 Z X1205S8I* X1205 I X1205S8IZ* (Note) X1205 Z I X1205V8* 1205 X1205V8Z* (Note) 1205 Z X1205V8I* 1205I ...

Page 3

ABSOLUTE MAXIMUM RATINGS Temperature Under Bias ................... -65°C to +135°C Storage Temperature ........................ -65°C to +150°C Voltage and IRQ CC BACK pin (respect to ground) ............................-0.5V to 7.0V Voltage on SCL, SDA, X1 and X2 pin ...

Page 4

Notes: (1) The device enters the Active state after any start, and remains active: for 9 clock cycles if the Device Select Bits in the Slave Address Byte are incorrect or until 200nS after a stop ending a read or ...

Page 5

AC Specifications (T = -40°C to +85°C, VCC = +2.7V to +5.5V, unless otherwise specified.) A Symbol f SCL Clock Frequency SCL t Pulse width Suppression Time at inputs IN t SCL LOW to SDA Data Out Valid AA t ...

Page 6

Write Cycle Timing SCL 8th Bit of Last Byte SDA Power-up Timing Symbol (1) t Time from Power-up to Read PUR (1) t Time from Power-up to Write PUW Notes: (1) Delays are measured from the time V V slew ...

Page 7

DESCRIPTION (continued) The powerful Dual Alarms can be set to any Clock/Calendar value for a match. For instance, every minute, every Tuesday March 21. The alarms can be polled in the Status Register or provide a ...

Page 8

ACK bit prior to RTC data output) into a separate latch to avoid time changes during the read operation. The clock continues to run. Alarms occurring during a read are unaffected by the read operation. Writing to the ...

Page 9

When there is a match, an alarm flag is set. The occur- rence of an alarm can be determined by polling the AL0 and AL1 bits or by enabling the IRQ output, using it as hardware flag. The alarm enable ...

Page 10

RTCF: Real Time Clock Fail Bit-Volatile This bit is set to a ‘1’ after a total power failure. This is a read only bit that is set by hardware (X1205 inter- nally) when the device powers up after having lost ...

Page 11

Unused Bits: This device does not use bits the SR, but must have a zero in these bit positions. The Data Byte output during a SR read will contain zeros in these bit locations. INTERRUPT CONTROL ...

Page 12

Write one to 8 bytes to the Clock/Control Registers with the desired clock, alarm, or control data. This sequence starts with a start bit, requires a ...

Page 13

Figure 4. Valid Data Changes on the SDA Bus SCL SDA Figure 5. Valid Start and Stop Conditions SCL SDA Figure 6. Acknowledge Response From Receiver SCL from Master Data Output from Transmitter Data Output from Receiver DEVICE ADDRESSING Following ...

Page 14

Figure 7. Slave Address, Word Address, and Data Bytes Write Operations Byte Write For a write operation, the device requires the Slave Address Byte and the Word Address ...

Page 15

Stop and Write Modes Stop conditions that terminate write operations must be sent by the master after sending at least 1 full data byte and it’s associated ACK signal stop is issued in the middle of a data ...

Page 16

Figure 10. Random Address Read Sequence S t Signals from a the Master Address r t SDA Bus Signals from the Slave Figure 11. Sequential Read Sequence Slave Signals from Address the Master SDA Bus Signals from ...

Page 17

APPLICATION SECTION CRYSTAL OSCILLATOR AND TEMPERATURE COMPENSATION Intersil has now integrated the oscillator compensation circuity on-chip, to eliminate the need for external components and adjust for crystal drift over tempera- ture and enable very high accuracy timekeeping (<5ppm drift). The ...

Page 18

A final application for the ATR control is in-circuit cali- bration for high accuracy applications, along with a temperature sensor chip. Once the RTC circuit is pow- ered up with battery backup, the PHZ output is set at 32.768kHz and ...

Page 19

Depending on the value of supercapacitor used, backup time can last from a few days to two weeks (with >1F). A simple silicon or Schottky barrier diode can be used in series with Vcc to charge the supercapacitor, which is ...

Page 20

Referring to Figure 13, Vtrip applies to the “Internal Vcc” node which powers the entire device. This means that if Vcc is powered down and the battery voltage at Vback is higher than the Vtrip voltage, then the entire chip ...

Page 21

PACKAGING INFORMATION Pin 1 Index 0.010 (0.25) 0.020 (0.50) 0° - 8° 0.016 (0.410) 0.037 (0.937) NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 21 X1205 8-Lead Plastic, SOIC, Package Code S8 Pin 1 0.014 (0.35) 0.019 (0.49) 0.188 ...

Page 22

... Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use ...

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