x1205s8izt1 Intersil Corporation, x1205s8izt1 Datasheet - Page 14

• Manufacturer Part Number: x1205s8izt1
• Description: 2-wire? Rtc Real Time Clock/calendar
• Manufacturer: Intersil Corporation

Figure 7. Slave Address, Word Address, and Data Bytes
Write Operations
Byte Write
For a write operation, the device requires the Slave
Address Byte and the Word Address Bytes. This gives
the master access to any one of the words in the CCR.
(Note: Prior to writing to the CCR, the master must
write a 02h, then 06h to the status register in two pre-
ceding operations to enable the write operation. See
“Writing to the Clock/Control Registers.” Upon receipt
of each address byte, the X1205 responds with an
Figure 8. Byte Write Sequence
A7
D7
1
Signals from
the Master
SDA Bus
Signals From
The Slave
0
D6
A6
1
0
14
A5
D5
0
0
S
a
t
r
t
A4
D4
1
1
0
1 0 1
Address
Slave
1
D3
A3
1
0
1
1
0
A
C
K
1
0 0 0 0 0 0 0 0
A2
D2
Address 1
0
X1205
Word
1
A1
D1
0
acknowledge. After receiving both address bytes the
X1205 awaits the eight bits of data. After receiving the
8 data bits, the X1205 again responds with an
acknowledge. The master then terminates the transfer
by generating a stop condition. The X1205 then
begins an internal write cycle of the data to the nonvol-
atile memory. During the internal write cycle, the
device inputs are disabled, so the device will not
respond to any requests from the master. The SDA out-
put is at high impedance. See Figure 8.
A
C
K
R/W
Address 0
A0
D0
0
Word
Slave Address Byte
Byte 0
Word Address 1
Byte 1
Word Address 0
Byte 2
Data Byte
Byte 3
A
C
K
Data
A
C
K
S
o
p
t
September 23, 2005
FN8097.2