x1205s8izt1 Intersil Corporation, x1205s8izt1 Datasheet - Page 13

• Manufacturer Part Number: x1205s8izt1
• Description: 2-wire? Rtc Real Time Clock/calendar
• Manufacturer: Intersil Corporation

Figure 4. Valid Data Changes on the SDA Bus
Figure 5. Valid Start and Stop Conditions
Figure 6. Acknowledge Response From Receiver
DEVICE ADDRESSING
Following a start condition, the master must output a
Slave Address Byte. Slave bits ‘1101’ access the CCR.
Bit 3 through Bit 1 of the slave byte specify the device
select bits. These are set to ‘111’.
The last bit of the Slave Address Byte defines the
operation to be performed. When this R/W bit is a one,
then a read operation is selected. A zero selects a
write operation. Refer to Figure 7.
After loading the entire Slave Address Byte from the
SDA bus, the X1205 compares the device identifier
and device select bits with ‘1101111’. Upon a correct
compare, the device outputs an acknowledge on the
SDA line.
SCL from
Master
Data Output
from Transmitter
Data Output
from Receiver
SCL
SDA
SDA
SCL
13
Start
Data Stable
Start
1
X1205
Data Change
Following the Slave Byte is a two byte word address.
The word address is either supplied by the master
device or obtained from an internal counter. On power-
up the internal address counter is set to address 0H,
so a current address read of the CCR array starts at
address 0. When required, as part of a random read,
the master must supply the 2 Word Address Bytes as
shown in Figure 7.
In a random read operation, the slave byte in the
“dummy write” portion must match the slave byte in
the “read” section. For a random read of the
Clock/Control Registers, the slave byte must be
1101111x in both places.
Data Stable
8
Stop
Acknowledge
9
September 23, 2005
FN8097.2