x1205s8izt1 Intersil Corporation, x1205s8izt1 Datasheet - Page 15

• Manufacturer Part Number: x1205s8izt1
• Description: 2-wire? Rtc Real Time Clock/calendar
• Manufacturer: Intersil Corporation

Stop and Write Modes
Stop conditions that terminate write operations must be
sent by the master after sending at least 1 full data byte
and it’s associated ACK signal. If a stop is issued in the
middle of a data byte, or before 1 full data byte + ACK is
sent, then the X1205 resets itself without performing the
write. The contents of the array are not affected.
Nonvolatile Write Polling
The resetting of the RWEL bit after a nonvolatile write
can be used to determine when the nonvolatile write is
complete. Once the stop condition is issued to indicate
the end of the master’s byte load operation, the X1205
initiates the internal nonvolatile write cycle. To begin
polling, the master begins reading the status register
to check the RWEL bit. If the X1205 is still busy with
the nonvolatile write cycle then the RWEL bit will
remain set to 1. When the X1205 has completed the
write operation, the RWEL bit will be set to 0.
Read Operations
There are three basic read operations: Current
Address Read, Random Read, and Sequential Read.
Current Address Read
Internally the X1205 contains an address counter that
maintains the address of the last word read incre-
mented by one. Therefore, if the last read was to
address n, the next read operation would access data
from address n+1. Upon receipt of the Slave Address
Byte with the R/W bit set to one, the X1205 issues an
acknowledge, then transmits eight data bits. The mas-
ter terminates the read operation by not responding
with an acknowledge during the ninth clock and issu-
ing a stop condition. Refer to Figure 9 for the address,
acknowledge, and data transfer sequence.
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condi-
tion during the ninth cycle or hold SDA HIGH during
the ninth clock cycle and then issue a stop condition.
Figure 9. Current Address Read Sequence
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Signals from
the Master
SDA Bus
Signals from
the Slave
S
a
t
r
t
1
1
Address
0
X1205
Slave
1
1
1
1
Random Read
Random read operations allow the master to access
any location in the X1205. Prior to issuing the Slave
Address Byte with the R/W bit set to zero, the master
must first perform a “dummy” write operation.
The master issues the start condition and the slave
address byte, receives an acknowledge, then issues
the word address bytes. After acknowledging receipt
of each word address byte, the master immediately
issues another start condition and the slave address
byte with the R/W bit set to one. This is followed by an
acknowledge from the device and then by the eight bit
data word. The master terminates the read operation
by not responding with an acknowledge and then issu-
ing a stop condition. Refer to Figure 10 for the
address, acknowledge, and data transfer sequence.
In a similar operation called “Set Current Address,” the
device sets the address if a stop is issued instead of
the second start shown in Figure 10. The X1205 then
goes into standby mode after the stop and all bus
activity will be ignored until a start is detected. This
operation loads the new address into the address
counter. The next Current Address Read operation will
read from the newly loaded address. This operation
could be useful if the master knows the next address it
needs to read, but is not ready for the data.
Sequential Read
Sequential reads can be initiated as either a current
address read or random address read. The first data
byte is transmitted as with the other modes; however,
the master now responds with an acknowledge, indi-
cating it requires additional data. The device continues
to output data for each acknowledge received. The
master terminates the read operation by not responding
with an acknowledge and then issuing a stop condition.
The data output is sequential, with the data from
address n followed by the data from address n + 1.
Refer to Figure 11 for the acknowledge and data
transfer sequence.
1
C
A
K
Data
S
o
p
t
September 23, 2005
FN8097.2